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參數資料
型號: AD7191BRUZ-REEL
廠商: Analog Devices Inc
文件頁數: 2/21頁
文件大小: 0K
描述: IC ADC 24BIT 2CH LN SD 24TSSOP
設計資源: Precision Weigh Scale Design Using AD7191 with Internal PGA (CN0118)
標準包裝: 2,500
位數: 24
采樣率(每秒): 120
數據接口: MICROWIRE?,QSPI?,串行,SPI?
轉換器數目: 1
電壓電源: 模擬和數字
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 24-TSSOP
包裝: 帶卷 (TR)
輸入數目和類型: 2 個差分,雙極
AD7191
Rev. A | Page 9 of 20
Pin No.
Mnemonic
Description
20
AVDD
Analog Supply Voltage, 3 V to 5.25 V. AVDD is independent of DVDD. Therefore, DVDD can be operated at 3 V
with AVDD at 5 V or vice versa.
21
DVDD
Digital Supply Voltage, 2.7 V to 5.25 V. DVDD is independent of AVDD. Therefore, AVDD can be operated at 3 V
with DVDD at 5 V or vice versa.
22
ODR1
Output Data Rate, Digital Input Pin. This pin is used with ODR2 to select the output data rate. See Table 5.
23
DOUT/RDY
Serial Data Output/Data Ready Output. DOUT/RDYserves a dual purpose. It functions as a serial data
output pin to access the data conversions from the ADC. In addition, DOUT/RDYoperates as a data ready
pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the
pin goes high before the next update occurs. The serial interface is reset each time that a conversion is
available. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data
is available. With an external serial clock, the data can be read using the DOUT/RDY pin. Data is placed on
the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge.
24
ODR2
Output Data Rate, Digital Input Pin. This pin is used with ODR1 to select the output data rate. See Table 5.
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