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| 型號(hào)： | AD7170BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 2/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT SIGMA-DELTA 10LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 125 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-WFDFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 10-LFCSP-WD（3x3） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸入數(shù)目和類型： | 2 個(gè)單端，雙極；1 個(gè)差分，雙極 |
| 產(chǎn)品目錄頁(yè)面： | 777 (CN2011-ZH PDF) |
| 其它名稱： | AD7170BCPZ-500RL7DKR AD7170BCPZ-500RL7DKR-ND AD7170BCPZ-REEL7DKR |
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AD7170
Data Sheet
Rev. A | Page 10 of 16
750
ADC CIRCUIT INFORMATION
OVERVIEW
The AD7170 is a low power ADC that incorporates a precision
12-bit Σ-Δ modulator and an on-chip digital filter intended for
measuring wide dynamic range, low frequency signals. The
device has an internal clock and one differential input. It
operates with an output data rate of 125 Hz and has a gain of 1.
A 2-wire interface simplifies data retrieval from the AD7170.
FILTER, DATA RATE, AND SETTLING TIME
The AD7170 uses a sinc3 filter. The output data rate is set to
125 Hz; thus, valid conversions are available every 1/125 = 8 ms.
If a reset occurs, then the user must allow the complete settling
time for the first conversion after the reset. The settling time is
equal to 24 ms. Subsequent conversions are available at 125 Hz.
When a step change occurs on the analog input, the AD7170
requires several conversion cycles to generate a valid conversion.
If the step change occurs synchronous to the conversion period,
then the settling time of the AD7170 must be allowed to generate
a valid conversion. If the step change occurs asynchronous to
the end of a conversion, then an extra conversion must be allowed
to generate a valid conversion. The data register is updated with
all the conversions but, for an accurate result, the user must
allow the required time.
Figure 12 shows the filter response of the filter. The only external
filtering required on the analog inputs is a simple R-C filter to
provide rejection at multiples of the master clock. A 1 KΩ
resistor in series with each analog input, a 0.01 μF capacitor
from each input to GND, and a 0.1 μF capacitor from AIN(+) to
AIN() are recommended.
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
625
500
375
250
125
FI
LT
E
R
G
A
IN
(
dB
)
INPUT SIGNAL FREQUENCY (Hz)
08
41
6-
0
11
Figure 12. Filter Response
GAIN
The AD7170 has a gain of 1. The acceptable analog input range
is +VREF. Therefore, with VREF = 5 V, the input range is +5 V.
POWER-DOWN/RESET(PDRST)
The PDRST pin functions as a power-down pin and a reset pin.
When PDRST is taken low, the AD7170 is powered down. The
entire ADC is powered down (including the on-chip clock), and
the DOUT/RDY pin is tristated. The circuitry and serial interface
are also reset. This resets the logic, the digital filter, and the analog
modulator. PDRST must be held low for 100 ns minimum to
initiate the reset function (see
).
When PDRST is taken high, the AD7170 is taken out of power-
down mode. When the on-chip clock has powered up (1 ms,
typically), the modulator then begins sampling the analog input.
The DOUT/RDY pin becomes active, going high until a valid
conversion is available. A reset is automatically performed on
power-up.
ANALOG INPUT CHANNEL
The AD7170 has one differential analog input channel that is
connected to the modulator; that is, the input is unbuffered.
Note that this unbuffered input path provides a dynamic load
to the driving source. Therefore, resistor/capacitor combinations
on the input pins can cause dc gain errors, depending on the
output impedance of the source that is driving the ADC input.
Table 7 shows the allowable external resistance/capacitance
values such that no gain error at the 12-bit level is introduced.
Table 7. External R-C Combination for No Gain Error
C (pF)
R (Ω)
50
9 k
100
6 k
500
1.5 k
1000
900
5000
200
The absolute input voltage range is restricted to a range between
GND 30 mV and VDD + 30 mV. Care must be taken in setting up
the common-mode voltage to avoid exceeding these limits. Other-
wise, there is degradation in linearity and noise performance.
BIPOLAR CONFIGURATION
The AD7170 accepts a bipolar input range. A bipolar input
range does not imply that the part can tolerate negative voltages
with respect to system GND. Signals on the AIN(+) input are
referenced to the voltage on the AIN() input. For example, if
AIN() is 2.5 V, the analog input range on the AIN(+) input is
0 V to 5 V when a 2.5 V reference is used.
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