參數(shù)資料
型號(hào): AD7156BCPZ-REEL
廠商: Analog Devices Inc
文件頁數(shù): 27/28頁
文件大?。?/td> 0K
描述: IC CDC 2CH 12BIT 1.8V 10-LFCSP
標(biāo)準(zhǔn)包裝: 5,000
類型: 電容數(shù)字轉(zhuǎn)換器
分辨率(位): 12 b
采樣率(每秒): 100k
數(shù)據(jù)接口: 串行
電壓電源: 單電源
電源電壓: 1.8 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-WFDFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 10-LFCSP-WD(3x3)
包裝: 帶卷 (TR)
AD7156
Rev. 0 | Page 8 of 2
0
50
100
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200
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300
CAPACITANCE CIN TO GROUND (pF)
TYPICAL PERFORMANCE CHARACTERISTICS
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
O
F
S
E
T
E
RRO
R
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p
F
)
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3.3V
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–1
–2
–3
–4
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O
F
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RRO
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)
CAPACITANCE EXC TO GROUND (pF)
07
72
6-
0
07
1.8V
3.3V
Figure 4. Capacitance Input Offset Error vs. Capacitance CIN to GND,
VDD = 1.8 V and 3.3 V, EXC Pin Open Circuit
Figure 7. Capacitance Input Offset Error vs. Capacitance EXC to GND,
VDD = 1.8 V and 3.3 V, CIN Pin Open Circuit
5
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–5
–10
–15
–20
G
A
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R)
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–25
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CAPACITANCE CIN TO GROUND (pF)
1.8V
3.3V
0
500
1000
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2000
G
A
IN
E
R
RO
R
(%
F
S
R)
CAPACITANCE EXC TO GROUND (pF)
07
72
6-
0
08
1.8V
3.3V
1
0
–1
–2
–3
–4
1
0
–1
–2
–3
–4
0
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G
A
IN
E
R
RO
R
(%
F
S
R)
CAPACITANCE EXC TO GROUND (pF)
07
72
6-
0
09
Figure 5. Capacitance Input Gain Error vs. Capacitance CIN to GND,
VDD = 1.8 V and 3.3 V, CIN to EXC = 3 pF
Figure 8. Capacitance Input Gain Error vs. Capacitance EXC to GND,
VDD = 1.8 V and 3.3 V, CIN to EXC = 3 pF
5
0
–5
–10
–15
–20
G
A
IN
E
R
RO
R
(%
F
S
R)
07
72
6-
0
06
–25
0
50
100
150
200
250
300
CAPACITANCE CIN TO GROUND (pF)
1.8V
3.3V
Figure 6. Capacitance Input Gain Error vs. Capacitance CIN to GND,
VDD = 1.8 V and 3.3 V, CIN to EXC = 9 pF
1.8V
3.3V
Figure 9. Capacitance Input Gain Error vs. Capacitance EXC to GND,
VDD = 1.8 V and 3.3 V, CIN to EXC = 9 pF
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