參數(shù)資料
型號： AD7143ACPZ-1500RL7
廠商： Analog Devices Inc
文件頁數(shù)： 36/57頁
文件大?。?/td> 0K
描述： IC CTLR PROGRAMMABLE CDC 16LFCSP
標(biāo)準(zhǔn)包裝： 1
類型： 電容數(shù)字轉(zhuǎn)換器
輸入類型： 邏輯
輸出類型： 邏輯
接口： I²C
電流 - 電源： 1mA
安裝類型： 表面貼裝
封裝/外殼： 16-VQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 16-LFCSP-VQ
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面： 781 (CN2011-ZH PDF)
其它名稱： AD7143ACPZ-1500RL7DKR
AD7143
Rev. 0 | Page 40 of 56
Table 23. STAGE_COMPLETE_INT_EN Register
Address
Data Bit
Default
Type
Name
Description
0x007
[0]
0
R/W
STAGE0_COMPLETE_EN
STAGE0 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE0 conversion
[1]
0
STAGE1_COMPLETE_EN
STAGE1 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE1 conversion
[2]
0
STAGE2_COMPLETE_EN
STAGE2 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE2 conversion
[3]
0
STAGE3_COMPLETE_EN
STAGE3 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE3 conversion
[4]
0
STAGE4_COMPLETE_EN
STAGE4 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE4 conversion
[5]
0
STAGE5_COMPLETE_EN
STAGE5 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE5 conversion
[6]
0
STAGE6_COMPLETE_EN
STAGE6 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE6 conversion
[7]
0
STAGE7_COMPLETE_EN
STAGE7 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE7 conversion
[11:8]
0
Unused
Set unused register bits = 0
[12]
0
TESTMODE
Set test mode register bits = 0 at all times
[15:13]
Unused
Set unused register bits = 0
Table 24. STAGE_LOW_LIMIT_INT Register1
Address
Data Bit
Default
Type
Name
Description
0x008
[0]
0
R
STAGE0_LOW_LIMIT_INT
STAGE0 CDC conversion low limit interrupt result
1 indicates STAGE0_LOW_THRESHOLD value exceeded
[1]
0
STAGE1_LOW_LIMIT_INT
STAGE1 CDC conversion low limit interrupt result
1 indicates STAGE1_LOW_THRESHOLD value exceeded
[2]
0
STAGE2_LOW_LIMIT_INT
STAGE2 CDC conversion low limit interrupt result
1 indicates STAGE2_LOW_THRESHOLD value exceeded
[3]
0
STAGE3_LOW_LIMIT_INT
STAGE3 CDC conversion low limit interrupt result
1 indicates STAGE3_LOW_THRESHOLD value exceeded
[4]
0
STAGE4_LOW_LIMIT_INT
STAGE4 CDC conversion low limit interrupt result
1 indicates STAGE4_LOW_THRESHOLD value exceeded
[5]
0
STAGE5_LOW_LIMIT_INT
STAGE5 CDC conversion low limit interrupt result
1 indicates STAGE5_LOW_THRESHOLD value exceeded
[6]
0
STAGE6_LOW_LIMIT_INT
STAGE6 CDC conversion low limit interrupt result
1 indicates STAGE6_LOW_THRESHOLD value exceeded
[7]
0
STAGE7_LOW_LIMIT_INT
STAGE7 CDC conversion low limit interrupt result
1 indicates STAGE7_LOW_THRESHOLD value exceeded
[15:8]
Unused
Set unused register bits = 0
1 Registers self-clear to 0 after readback, provided that the limits are not exceeded.
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