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參數(shù)資料
| 型號： | AD7143ACPZ-1500RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 26/57頁 |
| 文件大小： | 0K |
| 描述： | IC CTLR PROGRAMMABLE CDC 16LFCSP |
| 標準包裝： | 1 |
| 類型： | 電容數(shù)字轉(zhuǎn)換器 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | I²C |
| 電流 - 電源： | 1mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 16-LFCSP-VQ |
| 包裝： | 標準包裝 |
| 產(chǎn)品目錄頁面： | 781 (CN2011-ZH PDF) |
| 其它名稱： | AD7143ACPZ-1500RL7DKR |
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AD7143
Rev. 0 | Page 31 of 56
PCB DESIGN GUIDELINES
CAPACITIVE SENSOR BOARD MECHANICAL SPECIFICATIONS
Table 15.
Parameter
Symbol
Min
Typ
Max
Unit
Distance from Edge of Any Sensor to Edge of Metal Object
D1
1.0
mm
Distance Between Sensor Edges1
D2 = D3 = D4
0
mm
2-Layer, and Flex Circuit)
D5
1.0
mm
1 The distance is dependent on the application and the positioning of the switches relative to each other and with respect to the user’s finger positioning and handling.
Adjacent sensors, with 0 minimum space between them, are implemented differentially.
2 The 1.0 mm specification is meant to prevent direct sensor board contact with any conductive material. This specification does not guarantee no EMI coupling from
the controller board to the sensors. Address potential EMI coupling issues by placing a grounded metal shield between the capacitive sensor board and the main
controller board as shown in Figure 44.
SLIDER
BUTTONS
CAPACITIVE SENSOR
PRINTED CIRCUIT
D1
D3
D4
8-WAY
SWITCH
METAL OBJECT
D2
06
47
2-
0
39
Figure 42. Capacitive Sensor Board Mechanicals Top View
D5
CAPACITIVE SENSOR BOARD
GROUNDED METAL SHIELD
CONTROLLER PRINTED CIRCUIT BOARD OR METAL CASING
064
72
-04
0
Figure 43. Capacitive Sensor Board Mechanicals Side View
D5
CAPACITIVE SENSOR BOARD
CONTROLLER PRINTED CIRCUIT BOARD OR METAL CASING
06
47
2-
04
1
Figure 44. Capacitive Sensor Board with Grounded Shield
CHIP SCALE PACKAGES
The lands on the chip scale package (CP-16-13) are rectangular.
The printed circuit board pad for these should be 0.1 mm
longer than the package land length, and 0.05 mm wider than
the package land width. Center the land on the pad to maximize
the solder joint size.
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. To avoid shorting, provide a
clearance of at least 0.25 mm between the thermal pad and the
inner edges of the land pattern on the printed circuit board.
Thermal vias can be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias are
used, they should be incorporated in the thermal pad at a
1.2 mm pitch grid. The via diameter should be between 0.3 mm
and 0.33 mm, and the via barrel should be plated with 1 oz.
copper to plug the via.
Connect the printed circuit board thermal pad to GND.
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