參數(shù)資料
型號(hào): AD7142ACPZ-REEL
廠商: Analog Devices Inc
文件頁(yè)數(shù): 40/73頁(yè)
文件大?。?/td> 0K
描述: IC CAP-TO-DGTL CONV PROG 32LFCSP
標(biāo)準(zhǔn)包裝: 1
類(lèi)型: 電容數(shù)字轉(zhuǎn)換器
分辨率(位): 16 b
采樣率(每秒): 250k
數(shù)據(jù)接口: 串行
電壓電源: 單電源
電源電壓: 2.6 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤(pán),CSP
供應(yīng)商設(shè)備封裝: 32-LFCSP-VQ
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面: 781 (CN2011-ZH PDF)
其它名稱(chēng): AD7142ACPZ-REELDKR
AD7142
Rev. A | Page 44 of 72
Table 25. STAGE_HIGH_INT_EN Register
Address
Data Bit
Default Value
Type
Name
Description
0x006
[0]
0
R/W
STAGE0_HIGH_INT_EN
STAGE0 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE0 high threshold is exceeded
[1]
0
STAGE1_HIGH_INT_EN
STAGE1 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE1 high threshold is exceeded
[2]
0
STAGE2_HIGH_INT_EN
STAGE2 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE2 high threshold is exceeded
[3]
0
STAGE3_HIGH_INT_EN
STAGE3 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE3 high threshold is exceeded
[4]
0
STAGE4_HIGH_INT_EN
STAGE4 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE4 high threshold is exceeded
[5]
0
STAGE5_HIGH_INT_EN
STAGE5 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE5 high threshold is exceeded
[6]
0
STAGE6_HIGH_INT_EN
STAGE6 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE6 high threshold is exceeded
[7]
0
STAGE7_HIGH_INT_EN
STAGE7 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE7 high threshold is exceeded
[8]
0
STAGE8_HIGH_INT_EN
STAGE8 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE8 high threshold is exceeded
[9]
0
STAGE9_HIGH_INT_EN
STAGE9 sensor high interrupt enable l
0 = interrupt source disabled
1 = INT asserted if STAGE9 high threshold is exceeded
[10]
0
STAGE10_HIGH_INT_EN
STAGE10 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE10 high threshold is exceeded
[11]
0
STAGE11_HIGH_INT_EN
STAGE11 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE11 high threshold is exceeded
[15:12]
Unused
Set unused register bits = 0
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