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參數(shù)資料
| 型號： | AD7013ARS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | CMOS TIA IS-54 Baseband Receive Port |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO28 |
| 封裝： | SSOP-28 |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 591K |
| 代理商： | AD7013ARS |
REV. A
AD7013
–7–
RECEIVE SECTION TIMING
(V
AA
= +5 V
±
10%; V
DD
= +5 V
±
10%; AGND = DGND = 0 V,f
MCLK
= 6.2208 MHz;
T
A
= T
MIN
to T
MAX
, unless otherwise noted)
MCLK (I)
RxCLK (O)
RxFRAME (O)
RxDATA (O)
I MSB
I LSB
1
t
17
t
18
t
19
t
20
t
21
t
22
t
23
t
24
15-BIT
I WORD
I/Q
FLAG BIT
15-BIT
Q WORD
Q LSB
Q MSB
0
I/Q
FLAG BIT
Q LSB
DxCLK (O)
I MSB
FINAL IQ PAIR PRIOR
TO POWER DOWN
CR14
NOTE: (O) INDICATES AN OUTPUT, (I) INDICATES AN INPUT
0
I LSB
1
Q MSB
The last DxCLK edge which is
used to write to Command Reg
One, setting CR14 to One
The last DxCLK edge which is
used to write to Command Reg
One, setting CR14 to Zero
t
25
t
16
Figure 3. Receive Serial Interface Timing with 4
×
Sampling of the Symbol Rate (CR10 = 1)
Limit at
T
A
= –40
°
C to +85
°
C
Parameter
Units
Description
t
16
Power-Up Receive to RxCLK
CR13 = 0, Rx Offset Autocalibration On
CR13 = 1, Rx Offset Autocalibration Off
Propagation Delay from MCLK Rising Edge to RxCLK Rising Edge
10240t
1
6144t
1
30
85
2t
1
t
1
–20
t
1
–20
–10
10
32t
1
2t
1
–10
10
10t
1
64t
1
ns max
ns max
ns min
ns max
ns
ns min
ns min
ns min
ns max
ns
ns
ns min
ns max
ns min
ns max
t
17
t
18
t
19
t
20
t
21
RxCLK Cycle Time; CR10 = 1; 4
×
Sampling of the Symbol Rate
RxCLK High Pulse Width; CR10 = 1
RxCLK Low Pulse Width; CR10 = 1
RxCLK Rising Edge to RxFRAME Rising Edge
t
22
t
23
t
24
RxFRAME Cycle Time; CR10 = 1
RxFRAME High Pulse Width; CR10 = 1
RxDATA Valid After RxCLK Rising Edge
t
25
DxCLK Rising Edge to Last Falling Edge RxCLK
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
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| AD7015AST | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
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