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參數(shù)資料
| 型號： | AD7013ARS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | CMOS TIA IS-54 Baseband Receive Port |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO28 |
| 封裝： | SSOP-28 |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 591K |
| 代理商： | AD7013ARS |
–14–
REV. A
AD7013
Receive Offset Calibration
Included in the digital filter is a means by which receive signal
offsets may be calibrated out. Each channel of the digital low-pass
filter section has an offset register. The offset register can be made
to contain a value representing the dc offset of the preceding analog
circuitry. In normal operation, the value stored in the offset register
is subtracted from the filter output data before the data appears on
the serial output pin. By so doing, dc offsets in the I and Q
channels get calibrated out. Autocalibration or user calibration can
be selected. Autocalibration will remove internal offsets only while
user calibration allows the user to write to the offset register in
order to also remove external offsets.
The offset registers have enough resolution to hold the value of any
dc offset between
±
153 mV (1/8th of the input range). The 10-bit
offset register represents a twos-complement value which is mapped
to a 15-bit twos-complement word as shown in Figure 19. The
contents of the offset registers are subtracted from their respective
ADC samples.
D0
D8
D2
D13
D14
D1
D0
10-BIT
I OR Q
OFFSET
REGISTER
15-BIT
I OR Q
OFFSET
WORD
0
0
MSB
LSB
D9
D11
D12
D10
Figure 19. Position of the 10-Bit Offset Word Within the
15-Bit ADC Word
Receive Offset Adjust: Auto-Calibration (CR13 = 0)
If receive autocalibration has been selected (CR13 = 0), then the
AD7013 will initiate an autocalibration routine each time the
receive path is brought out of the low power sleep mode (CR14 =
0). The AD7013 internally disconnects the differential inputs from
the input pins and shorts the differential inputs to measure the
resulting ADC offset. This is then averaged 16 times to reduce
ADC noise, and the averaged result is then placed in the offset
register. The input to the ADC is then switched back for normal
operation, and after allowing for both analog settling and digital
filter settling, the first IQ sample pair is output (Figure 14).
Autocalibration will only remove on-chip offsets.
Receive Offset Adjust: User Calibration (CR13 = 1)
When user calibration has been selected, the receive offset register
can be written to, allowing offsets in the IF/RF demodulation
circuitry to be also calibrated out. However, the user is now
responsible for calibrating out receive offsets belonging to the
AD7013. When the receive path enters the low power mode
(CR14 = 0), the offset registers remain valid. After powering up,
the first IQ sample pair is output once time has elapsed for both the
analog circuitry to settle and also for the output of the digital filter
to settle as shown in Figure 15.
FREQUENCY – kHz
M
0
–100
–70
–90
–80
–40
–60
–50
–30
–20
–10
52.5
60.0
7.5
0.0
45.0
37.5
30.0
22.5
15.0
Figure 16. Receive Root Raised Cosine FIR Filter;
CR11 = 0, MCLK = 6.2208 MHz
FREQUENCY – kHz
M
0
–100
–70
–90
–80
–40
–60
–50
–30
–20
–10
52.5
60.0
7.5
0.0
45.0
37.5
30.0
22.5
15.0
Figure 17. Receive Analog Mode FIR Filter; CR11 = 1,
MCLK = 5.12 MHz
FREQUENCY – kHz
M
0
–100
–70
–90
–80
–40
–60
–50
–30
–20
–10
0.0
45.0
30.0
15.0
ANALOG MODE
FILTER RESPONSE
DIGITAL MODE
FILTER RESPONSE
Figure 18. Comparision of the Two Frequency Responses
Where Digital Mode was Clocked at 6.2208 MHz and
Analog Mode was Clocked at 5.12 MHz
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