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參數(shù)資料
| 型號(hào)： | AD673JNZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8BIT REF/CLK/COMP 20DIP |
| 標(biāo)準(zhǔn)包裝： | 18 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 33k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 20-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 20-PDIP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個(gè)單端，單極；1 個(gè)單端，雙極 |
AD673
REV. A
–7–
In systems where this read-write interface is used, at least
30 microseconds (the maximum conversion time) must be al-
lowed to pass between starting a conversion and reading the re-
sults. This delay or “time-out” period can be implemented in a
short software routine such as a countdown loop, enough
dummy instructions to consume 30 microseconds, or enough
actual useful instructions to consume the required time. In tightly-
timed systems, the DR line may be read through an external
three-state buffer to determine precisely when a conversion is
complete. Higher-speed systems may choose to use DR to signal
an interrupt to the processor at the end of a conversion.
Figure 12. Typical AD673 Timing Diagram
CONVERT Pulse Generation
The AD673 is tested with a CONVERT pulse width of 500 ns
and will typically operate with a pulse as short as 300 ns. How-
ever, some microprocessors produce active WR pulses which are
shorter than this. Either of the circuits shown in Figure 13 can
be used to generate an adequate CONVERT pulse for the
AD673. In both circuits, the short low-going WR pulse sets the
CONVERT line high through a flip-flop. The rising edge of DR
(which signifies that the internal logic has been reset) resets
the flip-flop and brings CONVERT low, which starts the
conversion.
Note that tDSC is slightly longer when the result of the previous
conversion contains a Logic 1 on the LSB. This means that the
actual CONVERT pulse generated by the circuits in Figure 13
will vary slightly in width.
Figure 13a. Using 74LS00
Figure 13b. Using 1/2 74LS74
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