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參數(shù)資料
| 型號(hào)： | AD670KNZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 3/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8BIT SGNL COND 20DIP |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 18 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 10k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 450mW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類(lèi)型： | 通孔 |
| 封裝/外殼： | 20-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 20-PDIP |
| 包裝： | 管件 |
| 輸入數(shù)目和類(lèi)型： | 1 個(gè)差分，單極；1 個(gè)差分，雙極 |
AD670
REV. A
–11–
Figure 17. Low Cost Sample-and-Hold Circuit for AD670
Since settling to 1/2 LSB at 8-bits of resolution requires 6.2 RC
time constants, the 500 pF hold capacitors and CD4066’s 300
on-resistance yield an acquisition time of under 1
s, assuming a
low impedance source.
This sample/hold approach makes use of the differential capa-
bilities of the AD670. Because 500 pF hold capacitors are used
on both VIN+ and VIN– inputs, the droop rate depends only on
the offset current of the AD670, typically 20 nA. With the
matched 500 pF capacitors, the droop rate is 40
V/s. The in-
put will then droop only 0.4 mV (0.4 LSB) during the AD670’s
10
s conversion time. The differential approach also minimizes
pedestal error since only the difference in charge injection be-
tween the two switches results in errors at the A/D.
The fast conversion time and differential and common-mode ca-
pabilities of the AD670 permit this simple sample-hold design
to perform well with low sample-to-hold offset, droop rate of
about 40
V/s and acquisition time under 1 s. The effective
aperture time of the AD670 is reduced by about 2 orders of
magnitude with this circuit, allowing frequencies to be con-
verted up to several kilohertz.
While no input anti-aliasing filter is shown, filtering will be nec-
essary to prevent output errors if higher frequencies are present
in the input signal. Many practical variations are possible with
this circuit, including input MUX control, for digitizing a num-
ber of ac channels.
IBM PC INTERFACE
The AD670 appears in Figure 18 interfaced to the IBM PC.
Since the device resides in I/O space, its address is decoded
from only the lower ten address lines and must be gated with
AEN (active low) to mask out internal (DMA) cycles which use
the same I/O address space. This active low signal is applied to
CS
. AO, meanwhile, is reserved for the R/W input. This places
the AD670 in two adjacent addresses; one for starting the con-
version and the other for reading the result. The IOR and IOW
signals are then gated and applied to CE, while the lower two
data lines are applied to FORMAT and BPO/UPO inputs to
provide software programmable input formats and output
coding.
In BASIC, a simple OUT ADDR, WORD command initiates a
conversion. While the upper six bits of the data WORD are
meaningless, the lower two bits define the analog input format
and digital output coding according to Table IV. The data is
available ten microseconds later (which is negligible in BASIC)
and can be read using INP (ADDR + 1). The 3-line subroutine
in Figure 19, used in conjunction with the interface of Figure
18, converts an analog input within a bipolar range to an offset
binary coded digital word.
Figure 18. IBM PC lnterface to AD670
NOTE: Due to the large number of options that may be in-
stalled in the PC, the I/O bus loading should be limited to one
Schottky TTL load. Therefore, a buffer/driver should be used
when interfacing more than two AD670s to the I/O bus.
Table IV.
Data
Input Format
Output Coding
0
Unipolar
Straight Binary
1
Bipolar
Offset Binary
2
Unipolar
2s Complement
3
Bipolar
2s Complement
10
OUT & H310,1
’INITIATE CONVERSION
20
ANALOGIN = INP (&H311)
’READ ANALOG INPUT
30
RETURN
Figure 19. Conversion Subroutine
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