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參數(shù)資料
| 型號(hào)： | AD670KNZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 10/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8BIT SGNL COND 20DIP |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 18 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 10k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 450mW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 20-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 20-PDIP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個(gè)差分，單極；1 個(gè)差分，雙極 |
AD670
REV. A
–7–
Table III. AD670 TIMING SPECIFICATIONS
@ +25 C
Symbol
Parameter
Min
Typ
Max
Units
WRITE/CONVERT START MODE
tW
Write/Start Pulse Width
300
ns
tDS
Input Data Setup Time
200
ns
tDH
Input Data Hold
10
ns
tRWC
Read/Write Setup Before Control
0
ns
tDC
Delay to Convert Start
700
ns
tC
Conversion Time
10
s
READ MODE
tR
Read Time
250
ns
tSD
Delay from Status Low to Data Read
250
ns
tTD
Bus Access Time
200
250
ns
tDH
Data Hold Time
25
ns
tDT
Output Float Delay
150
ns
tRT
R/W before CE or CS low
0
ns
Boldface indicates parameters tested 100% unless otherwise noted. See Specifications page for explanation.
6b. Bipolar
6c. Full Scale (Unipolar)
Figure 6. Transfer Curves
CONTROL AND TIMING OF THE AD670
Control Logic
The AD670 contains on-chip logic to provide conversion and
data read operations from signals commonly available in micro-
processor systems. Figure 7 shows the internal logic circuitry of
the AD670. The control signals, CE, CS, and R/W control the
operation of the converter. The read or write function is deter-
mined by R/W when both CS and CE are low as shown in
Table II. If all three control inputs are held low longer than the
conversion time, the device will continuously convert until one
input, CE, CS, or R/W is brought high. The relative timing of
these signals is discussed later in this section.
Figure 7. Control Logic Block Diagram
Table II. AD670 Control Signal Truth Table
R/W
CS
CE
OPERATION
0
WRITE/CONVERT
1
0
READ
X
1
NONE
X
1
X
NONE
Timing
The AD670 is easily interfaced to a variety of microprocessors
and other digital systems. The following discussion of the timing
requirements of the AD670 control signals will provide the de-
signer with useful insight into the operation of the device.
Write/Convert Start Cycle
Figure 8 shows a complete timing diagram for the write/convert
start cycle. CS (chip select) and CE (chip enable) are active low
and are interchangeable signals. Both CS and CE must be low
for the converter to read or start a conversion. The minimum
pulse width, tW, on either CS or CE is 300 ns to start a
conversion.
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