參數(shù)資料
型號: AD6654CBC
廠商: Analog Devices Inc
文件頁數(shù): 3/88頁
文件大?。?/td> 0K
描述: IC ADC 14BIT W/4CH RSP 256CSPBGA
標準包裝: 1
位數(shù): 14
采樣率(每秒): 92.16M
數(shù)據(jù)接口: 串行,并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 2.5W
電壓電源: 模擬和數(shù)字
工作溫度: -25°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 256-BGA,CSPBGA
供應商設備封裝: 256-CSPBGA(17x17)
包裝: 托盤
輸入數(shù)目和類型: 1 個差分,單極
AD6654
Rev. 0 | Page 11 of 88
SERIAL PORT TIMING CHARACTERISTICS
Table 9.
Temp
Test Level
Min
Typ
Max
Unit
SERIAL PORT CLOCK TIMING REQUIREMENTS
tSCLK
SCLK Period
Full
IV
10.0
ns
tSCLKL
SCLK Low Time
Full
IV
1.60
0.5 × tSCLK
ns
tSCLKH
SCLK High Time
Full
IV
1.60
0.5 × tSCLK
ns
SPI PORT CONTROL TIMING REQUIREMENTS (MODE = 0)
tSSDI
SDI to
↑SCLK Setup Time
Full
IV
1.30
ns
tHSDI
SDI to
↑SCLK Hold Time
Full
IV
0.40
ns
tSSCS
SCS to
↑SCLK Setup Time
Full
IV
4.12
ns
tHSCS
SCS to
↑SCLK Hold Time
Full
IV
2.78
ns
tDSDO
↑SCLK to SDO Delay Time
Full
IV
4.28
7.96
ns
SPORT MODE CONTROL TIMING REQUIREMENTS (MODE = 1)
tSSDI
SDI to
↑SCLK Setup Time
Full
IV
0.80
ns
tHSDI
SDI to
↑SCLK Hold Time
Full
IV
0.40
ns
tSSRFS
SRFS to
↓SCLK Setup Time
Full
IV
1.60
ns
tHSRFS
SRFS to
↓SCLK Hold Time
Full
IV
0.13
ns
tSSTFS
STFS to
↓SCLK Setup Time
Full
IV
1.60
ns
tHSTFS
STFS to
↓SCLK Hold Time
Full
IV
0.30
ns
tSSCS
SCS to
↑SCLK Setup Time
Full
IV
4.12
ns
tHSCS
SCS to
↑SCLK Hold Time
Full
IV
2.76
ns
tDSDO
↑SCLK to SDO Delay Time
Full
IV
4.29
7.95
ns
1 All timing specifications are valid over the VDDCORE range of 1.7 V to 1.9 V and the VDDIO range of 3.0 V and 3.6 V.
2 CLOAD = 40 pF on all outputs, unless otherwise noted.
3 SCLK rise/fall time should be 3 ns maximum.
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