參數(shù)資料
型號: AD6645ASVZ-105
廠商: Analog Devices Inc
文件頁數(shù): 1/24頁
文件大小: 0K
描述: IC ADC 14BIT 105MSPS 52TQFP
設(shè)計資源: Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109)
標(biāo)準(zhǔn)包裝: 1
位數(shù): 14
采樣率(每秒): 105M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 4
功率耗散(最大): 1.75W
電壓電源: 模擬和數(shù)字
工作溫度: -10°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 52-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 52-TQFP-EP(10x10)
包裝: 托盤
輸入數(shù)目和類型: 1 個差分,雙極
14-Bit, 80 MSPS/105 MSPS
A/D Converter
AD6645
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2002–2008 Analog Devices, Inc. All rights reserved.
FEATURES
SNR = 75 dB, fIN 15 MHz, up to 105 MSPS
SNR = 72 dB, fIN 200 MHz, up to 105 MSPS
SFDR = 89 dBc, fIN 70 MHz, up to 105 MSPS
100 dBFS multitone SFDR
IF sampling to 200 MHz
Sampling jitter: 0.1 ps
1.5 W power dissipation
Differential analog inputs
Pin compatible to AD6644
Twos complement digital output format
3.3 V CMOS compatible
Data-ready for output latching
APPLICATIONS
Multichannel, multimode receivers
Base station infrastructures
AMPS, IS-136, CDMA, GSM, W-CDMA
Single channel digital receivers
Antenna array processing
Communications instrumentation
Radars, infrared imaging
Instrumentation
GENERAL DESCRIPTION
The AD6645 is a high speed, high performance, monolithic 14-bit
analog-to-digital converter (ADC). All necessary functions,
including track-and-hold (T/H) and reference, are included on the
chip to provide a complete conversion solution. The AD6645
provides CMOS-compatible digital outputs. It is the fourth
generation in a wideband ADC family, preceded by the AD9042
(12-bit, 41 MSPS), the AD6640 (12-bit, 65 MSPS, IF sampling),
and the AD6644 (14-bit, 40 MSPS/65 MSPS).
Designed for multichannel, multimode receivers, the AD6645 is
part of the Analog Devices, Inc., SoftCell transceiver chipset.
The AD6645 maintains 100 dB multitone, spurious-free dynamic
range (SFDR) through the second Nyquist band. This breakthrough
performance eases the burden placed on multimode digital
receivers (software radios) that are typically limited by the ADC.
Noise performance is exceptional; typical signal-to-noise ratio
(SNR) is 74.5 dB through the first Nyquist band.
The AD6645 is built on the Analog Devices extra fast
complementary bipolar (XFCB) process and uses an innovative,
multipass circuit architecture. Units are available in thermally
enhanced 52-lead PowerQuad 4 (LQFP_PQ4) and 52-lead
exposed pad (TQFP_EP) packages specified from 40°C to
+85°C at 80 MSPS and 10°C to +85°C at 105 MSPS.
PRODUCT HIGHLIGHTS
1.
IF Sampling. The AD6645 maintains outstanding ac
performance up to input frequencies of 200 MHz, suitable
for multicarrier 3G wideband cellular IF sampling receivers.
2.
Pin Compatibility. The ADC has the same footprint and
pin layout as the AD6644 14-bit, 40 MSPS/65 MSPS ADC.
3.
SFDR Performance and Oversampling. Multitone SFDR
performance of 100 dBFS can reduce the requirements of
high end RF components and allows the use of receive
signal processors, such as the AD6620, AD6624/AD6624A,
FUNCTIONAL BLOCK DIAGRAM
5
6
5
AD6645
AIN
VREF
ENCODE
GND
DMID
OVR
DRY
D13
MSB
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
LSB
ADC3
TH5
TH4
DAC2
ADC2
TH3
A2
DAC1
DIGITAL ERROR CORRECTION LOGIC
TH2
ADC1
TH1
A1
2.4V
INTERNAL
TIMING
DVCC
AVCC
02
64
7-
00
1
Figure 1.
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