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參數(shù)資料
| 型號： | AD6459 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | GSM 3 V Receiver IF Subsystem |
| 中文描述： | 3伏的GSM接收機(jī)中頻子系統(tǒng) |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 314K |
| 代理商： | AD6459 |
AD6459
–7–
REV. 0
PLL FREQUENCY – MHz
F
R
P
–0.1
–1.5
5
55
10
15
20
25
30
35
40
45
50
–0.3
–0.5
–0.7
–0.9
–1.1
–1.3
Figure 15. PLL Loop Voltage at FLTR Pin (KVCO) vs.
Frequency
GAIN VOLTAGE – Volts
–10
I
R
–20
–80
0.5
2.5
1.0
1.5
2.0
–40
–50
–60
–70
–30
Figure 16. System (Mixer + IF LC Filter +IF Amplifier +
Demodulator) 1 dB Compression Point vs. Gain,
T
A
= +25
°
C, V
POS
= 2.7 V, F
IF
= 13 MHz, V
REF
= 1.2 V
GAIN VOLTAGE – Volts
–10
–20
0
0.5
2.5
1.0
1.5
2.0
–40
–50
–60
–70
–30
I
Figure 17. System (Mixer + IF LC Filter + I F Amplifier +
Demodulator) IP3 vs. Gain, T
A
= +25
°
C, V
POS
= 2.7 V,
IF = 13 MHz, V
REF
= 1.2 V
GAIN VOLTAGE – Volts
S
18
16
40
2.5
0.5
1
1.5
2
12
10
8
6
14
V
POS
= 2.7V, T
A
= +85
°
C
V
POS
= 2.7V, T
A
= +25
°
C
V
POS
= 5.5V, T
A
= +85
°
C
V
POS
= 5.5V, T
A
= +25
°
C
V
POS
= 5.5V, T
A
= –40
°
C
Figure 18. Power Supply Current vs. Gain Control
Voltage, V
REF
= 1.2 V
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|---|---|
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| AD645B | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Noise, Low Drift FET Op Amp |
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