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| 型號： | AD603ARZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP VGA 90MHZ LN 50MA 8SOIC |
| 標準包裝： | 750 |
| 系列： | X-AMP® |
| 放大器類型： | 可變增益 |
| 電路數(shù)： | 1 |
| 轉(zhuǎn)換速率： | 275 V/µs |
| -3db帶寬： | 90MHz |
| 電流 - 輸入偏壓： | 200nA |
| 電流 - 電源： | 12.5mA |
| 電流 - 輸出 / 通道： | 50mA |
| 電壓 - 電源，單路/雙路(±)： | 9.5 V ~ 12.6 V，±4.75 V ~ 6.3 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 包裝： | 帶卷 (TR) |
| 配用： | AD603-EVALZ-ND - BOARD EVALUATION FOR AD603 |
AD603
Data Sheet
Rev. K | Page 16 of 24
The gains are offset (Figure 41) such that the gain of A2 is
increased only after the gain of A1 has reached its maximum
value. Note that for a differential input of –600 mV or less, the
gain of a single amplifier (A1 or A2) is at its minimum value of
11.07 dB; for a differential input of 600 mV or more, the gain
is at its maximum value of 31.07 dB. Control inputs beyond
these limits do not affect the gain and can be tolerated without
damage or foldover in the response. This is an important aspect
of the gain control response of the AD603. (See the Specifications
section for more details on the allowable voltage range.) The
gain is now
Gain (dB) = 40 VG + GO
(3)
where:
VG is the applied control voltage.
GO is determined by the gain range chosen.
In the explanatory notes that follow, it is assumed that
the maximum bandwidth connections are used, for which
GO is 20 dB.
+31.07dB
+10dB
A1
A2
+31.07dB
+28.96dB
–11.07dB
0.473
1.526
–8.93dB
0
–20
0.5
0
1.0
20
1.50
40
2.0
60
VC (V)
62.14
–22.14
GAIN
(dB)
*GAIN OFFSET OF 1.07dB, OR 26.75mV.
00
53
9-
0
39
*
Figure 41. Explanation of Offset Calibration for Sequential Control
With reference to Figure 38, Figure 39, and Figure 40, note that
VG1 refers to the differential gain control input to A1, and VG2
refers to the differential gain control input to A2. When VG is
0 V, VG1 = 473 mV and thus the gain of A1 is 8.93 dB (recall
that the gain of each individual amplifier in the maximum
bandwidth mode is –10 dB for VG = 500 mV and 10 dB for VG
= 0 V); meanwhile, VG2 = 1.908 V so the gain of A2 is pinned
at 11.07 dB. The overall gain is therefore –20 dB (see Figure 38).
When VG = 1.00 V, VG1 = 1.00 V 0.473 V = 0.526 V, which sets
the gain of A1 to nearly its maximum value of +31.07 dB, while
VG2 = 1.00 V 1.526 V = 0.526 V, which sets the gain of A2 to
nearly its minimum value of 11.07 dB. Close analysis shows
that the degree to which neither AD603 is completely pushed to
its maximum nor minimum gain exactly cancels in the overall
gain, which is now 20 dB (see Figure 39).
When VG = 2.0 V, the gain of A1 is pinned at 31.07 dB and that
of A2 is near its maximum value of 28.93 dB, resulting in an
overall gain of 60 dB (see Figure 40). This mode of operation is
further clarified in Figure 42, which is a plot of the separate
gains of A1 and A2 and the overall gain vs. the control voltage.
Figure 43 is a plot of the SNR of the cascaded amplifiers vs. the
control voltage. Figure 44 is a plot of the gain error of the
cascaded stages vs. the control voltages.
00
53
9-
0
4
0
VC (V)
2.0
–0.2
0.2
0.6
1.0
1.4
1.8
OV
E
R
A
L
G
A
IN
(
d
B
)
70
50
60
40
30
20
10
0
–10
–20
–30
COMBINED
A1
A2
Figure 42. Plot of Separate and Overall Gains in Sequential Control
00
53
9-
0
4
1
VC (V)
2.0
–0.2
0.2
0.6
1.0
1.4
1.8
S
NR
(
d
B)
90
80
70
60
50
40
30
20
10
Figure 43. SNR for Cascaded Stages—Sequential Control
00
53
9-
0
4
2
VC (V)
2.2
–0.2
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
G
AI
N
E
R
RO
R
(
d
B)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
Figure 44. Gain Error for Cascaded Stages–Sequential Control
PARALLEL MODE (SIMPLEST GAIN CONTROL
INTERFACE)
In this mode, the gain control of voltage is applied to both
inputs in parallel: the GPOS pins of both A1 and A2 are
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