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參數(shù)資料
| 型號： | AD598JR |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LVDT SGNL COND OSC/REF 20SOIC |
| 標準包裝： | 1 |
| 類型： | 信號調節(jié)器 |
| 輸入類型： | 電壓 |
| 輸出類型： | 電壓 |
| 接口： | LVDT |
| 電流 - 電源： | 15mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 20-SOIC W |
| 包裝： | 管件 |
AD598
REV. A
–5–
a voltage proportional to position. This technique uses the pri-
mary excitation voltage as a phase reference to determine the
polarity of the output voltage. There are a number of problems
associated with this technique such as (1) producing a constant
amplitude, constant frequency excitation signal, (2) compensating
for LVDT primary to secondary phase shifts, and (3) compen-
sating for these shifts as a function of temperature and frequency.
The AD598 eliminates all of these problems. The AD598 does
not require a constant amplitude because it works on the ratio of
the difference and sum of the LVDT output signals. A constant
frequency signal is not necessary because the inputs are rectified
and only the sine wave carrier magnitude is processed. There is
no sensitivity to phase shift between the primary excitation and
the LVDT outputs because synchronous detection is not em-
ployed. The ratiometric principle upon which the AD598 oper-
ates requires that the sum of the LVDT secondary voltages
remains constant with LVDT stroke length. Although LVDT
manufacturers generally do not specify the relationship between
VA+VB and stroke length, it is recognized that some LVDTs do
not meet this requirement. In these cases a nonlinearity will
result. However, the majority of available LVDTs do in fact
meet these requirements.
The AD598 utilizes a special decoder circuit. Referring to the
block diagram and Figure 6 below, an implicit analog comput-
ing loop is employed. After rectification, the A and B signals are
multiplied by complementary duty cycle signals, d and (I–d)
respectively. The difference of these processed signals is inte-
grated and sampled by a comparator. It is the output of this
comparator that defines the original duty cycle, d, which is fed
back to the multipliers.
As shown in Figure 6, the input to the integrator is [(A+B)d]B.
Since the integrator input is forced to 0, the duty cycle d =
B/(A+B).
The output comparator which produces d = B/(A+B) also con-
trols an output amplifier driven by a reference current. Duty
cycle signals d and (1–d) perform separate modulations on the
reference current as shown in Figure 6, which are summed. The
summed current, which is the output current, is IREF
× (1–2d).
Since d = B/(A+B), by substitution the output current equals
IREF × (A–B)/(A+B). This output current is then filtered and
converted to a voltage since it is forced to flow through the scal-
ing resistor R2 such that:
V
OUT
= I
REF × ( A – B )/( A + B ) × R 2
CONNECTING THE AD598
The AD598 can easily be connected for dual or single supply
operation as shown in Figures 7 and 12. The following general
design procedures demonstrate how external component values
are selected and can be used for any LVDT which meets AD598
input/output criteria.
Parameters which are set with external passive components in-
clude: excitation frequency and amplitude, AD598 system
bandwidth, and the scale factor (V/inch). Additionally, there are
optional features, offset null adjustment, filtering, and signal in-
tegration which can be used by adding external components.
COMP
FILT
∑
COMP
∑
RTO
OFFSET
FILT
∑
INTEG
V TO I
BANDGAP
REFERENCE
INPUT
±1
A
d
B
0<d<1
BINARY SIGNAL
d - DUTY CYCLE
(A+B) d–B
q
B
A+B
1–d
I
REF
d
I
REF q
A–B
A+B
VOLTS
OUTPUT
VOUT = RSCALE x I REF x
A–B
A+B
INTEG
V TO I
1–d
d
V TO I
Figure 6. Block Diagram of Decoder
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD598JRZ | 功能描述:IC LVDT SGNL COND OSC/REF 20SOIC RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關文件:Automotive Product Guide 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:20-TSSOP 包裝:管件 |
| AD598JRZ | 制造商:Analog Devices 功能描述:Signal Conditioner IC |
| AD598SD/883B | 制造商:Analog Devices 功能描述:LVDT Signal Conditioner 20-Pin SBCDIP 制造商:Analog Devices 功能描述:LVDT IC - Rail/Tube 制造商:Analog Devices 功能描述:MIL LVDT SIG COND 20-CDIP 制造商:Analog Devices 功能描述:IC SIGNAL CONDITIONER 制造商:Analog Devices Inc. 功能描述:Interface - Specialized IC LVDT Signal Conditioner |
| AD598SD/883B-MOOG | 制造商:Analog Devices 功能描述: |
| AD5T | 制造商:Opto 22 功能描述:I/O Module; 5 VDC @ 170 mA; 0 to degC; UL, CSA, CE Certified 制造商:Opto 22 功能描述:I/O MODULE 制造商:Opto 22 功能描述:I/O MODULE; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; No. of Analog Inputs:1; No. of Digital Outputs:1; No. of Outputs:1; Resolution:12 Bits; Signal Input Type:J Thermocouple ;RoHS Compliant: No 制造商:Opto 22 功能描述:Access Module Analog J Thermocouple Input Isolated Ad5T |
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