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參數資料
| 型號： | AD598JR |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 16/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LVDT SGNL COND OSC/REF 20SOIC |
| 標準包裝： | 1 |
| 類型： | 信號調節(jié)器 |
| 輸入類型： | 電壓 |
| 輸出類型： | 電壓 |
| 接口： | LVDT |
| 電流 - 電源： | 15mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 20-SOIC W |
| 包裝： | 管件 |
AD598
REV. A
–9–
Figure 15. Gain and Phase Characteristics vs. Frequency
(0 kHz–10 kHz)
1000
100
10
1
0.1
0.01
0.1
1
10
C2, C3, C4; C2 = C3 = C4 –
F
RIPPLE
–
mV
rms
2.5kHz, C
SHUNT = 0nF
2.5kHz, C
SHUNT = 1nF
2.5kHz, C
SHUNT =10nF
Figure 16. Output Voltage Ripple vs. Filter Capacitance
1000
100
10
1
0.1
0.001
0.01
0.1
110
C2, C3, C4; C2 = C3 = C4 –
F
RIPPLE
–
mV
rms
10kHz , C SHUNT = 0nF
10kHz , C SHUNT = 1nF
10kHz , C SHUNT = 10nF
Figure 17. Output Voltage Ripple vs. Filter Capacitance
Determining LVDT Sensitivity
LVDT sensitivity can be determined by measuring the LVDT
secondary voltages as a function of primary drive and core posi-
tion, and performing a simple computation.
Energize the LVDT at its recommended primary drive level,
VPRI (3 V rms for the E100). Set the core to midpoint where
VA = VB. Set the core displacement to its mechanical full-scale
position and measure secondary voltages VA and VB.
Sensitivity
=
VA(at Full Scale )– VB (at Full Scale )
VPRI × d
From Figure 18,
Sensitivity
=
1.71 – 0.99
3
× 100 mils =
2.4 mV/V/mil
d = –100 mils
d = 0
A
V
VB
1.71V rms
0.99V rms
100 mils
+
d =
VSEC WHEN VPRI = 3V rms
Figure 18. LVDT Secondary Voltage vs. Core Displacement
Thermal Shutdown and Loading Considerations
The AD598 is protected by a thermal overload circuit. If the die
temperature reaches 165
°C, the sine wave excitation amplitude
gradually reduces, thereby lowering the internal power dissipa-
tion and temperature.
Due to the ratiometric operation of the decoder circuit, only
small errors result from the reduction of the excitation ampli-
tude. Under these conditions the signal-processing section of
the AD598 continues to meet its output specifications.
The thermal load depends upon the voltage and current deliv-
ered to the load as well as the power supply potentials. An
LVDT Primary will present an inductive load to the sine wave
excitation. The phase angle between the excitation voltage and
current must also be considered, further complicating thermal
calculations.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD598JRZ | 功能描述:IC LVDT SGNL COND OSC/REF 20SOIC RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關文件:Automotive Product Guide 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數字 輸出類型:數字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:20-TSSOP 包裝:管件 |
| AD598JRZ | 制造商:Analog Devices 功能描述:Signal Conditioner IC |
| AD598SD/883B | 制造商:Analog Devices 功能描述:LVDT Signal Conditioner 20-Pin SBCDIP 制造商:Analog Devices 功能描述:LVDT IC - Rail/Tube 制造商:Analog Devices 功能描述:MIL LVDT SIG COND 20-CDIP 制造商:Analog Devices 功能描述:IC SIGNAL CONDITIONER 制造商:Analog Devices Inc. 功能描述:Interface - Specialized IC LVDT Signal Conditioner |
| AD598SD/883B-MOOG | 制造商:Analog Devices 功能描述: |
| AD5T | 制造商:Opto 22 功能描述:I/O Module; 5 VDC @ 170 mA; 0 to degC; UL, CSA, CE Certified 制造商:Opto 22 功能描述:I/O MODULE 制造商:Opto 22 功能描述:I/O MODULE; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; No. of Analog Inputs:1; No. of Digital Outputs:1; No. of Outputs:1; Resolution:12 Bits; Signal Input Type:J Thermocouple ;RoHS Compliant: No 制造商:Opto 22 功能描述:Access Module Analog J Thermocouple Input Isolated Ad5T |
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