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參數(shù)資料
| 型號： | AD5749ACPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 27/28頁 |
| 文件大小： | 0K |
| 描述： | IC CURRENT OUT DVR 32-LFCSP |
| 標準包裝： | 1 |
| 放大器類型： | 儀表 |
| 電路數(shù)： | 1 |
| 電流 - 電源： | 5.2mA |
| 電流 - 輸出 / 通道： | 24mA |
| 電壓 - 電源，單路/雙路(±)： | 10.8 V ~ 55 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 標準包裝 |
| 其它名稱： | AD5749ACPZ-RL7DKR |
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AD5749
Data Sheet
Rev. B | Page 8 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
SDO/VFAULT
Serial Data Output (SDO). In software mode, this pin is used to clock data from the input shift register in
readback mode. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK.
This pin is a CMOS output.
2
CLRSEL
In hardware or software mode, this pin selects the clear value, either zero scale or midscale. In software
mode, this pin is implemented as a logic OR with the internal CLRSEL bit.
3
CLEAR
Active High Input. Asserting this pin sets the output current to zero-scale code or midscale of range
selected (user selectable). CLEAR is a logic OR with the internal CLEAR bit. See the Asynchronous Clear
(CLEAR) section for more details.
4
DVCC
Digital Power Supply.
5
GND
Ground Connection.
6
SYNC/RSET
Positive Edge-Sensitive Latch (SYNC). In software mode, a rising edge parallel loads the input shift
register data into the AD5749 and also updates the output.
Resistor Select (RSET). In hardware mode, this pin selects whether the internal or the external current
sense resistor is used.
If RSET = 0, the external sense resistor is chosen.
If RSET = 1, the internal sense resistor is chosen.
7
SCLK/OUTEN
Serial Clock Input (SCLK). In software mode, data is clocked into the input shift register on the falling
edge of SCLK. This pin operates at clock speeds up to 50 MHz.
Output Enable (OUTEN). In hardware mode, this pin acts as an output enable pin.
8
SDIN/R0
Serial Data Input (SDIN). In software mode, data must be valid on the falling edge of SCLK.
Range Decode Bit (R0). In hardware mode, this pin, in conjunction with R1, R2, and R3, selects the output
current range setting on the part.
9
AD2/R1
Device Addressing Bit (AD2). In software mode, this pin, in conjunction with AD0 and AD1, allows up to
eight devices to be addressed on one bus.
Range Decode Bit (R1). In hardware mode, this pin, in conjunction with R0, R2, and R3, selects the output
current range setting on the part.
10
AD1/R2
Device Addressing Bit (AD1). In software mode, this pin, in conjunction with AD0 and AD2, allows up to
eight devices to be addressed on one bus.
Range Decode Bit (R2). In hardware mode, this pin, in conjunction with R0, R1, and R3, selects the output
current range setting on the part.
11
AD0/R3
Device Addressing Bit (AD0). In software mode, this pin, in conjunction with AD1 and AD2, allows up to
eight devices to be addressed on one bus.
Range Decode Bit (R3). In hardware mode, this pin, in conjunction with R0, R1, and R2, selects the output
current range setting on the part.
PIN 1
INDICATOR
TOP VIEW
(Not to Scale)
AD5749
1
SDO/VFAULT
2
CLRSEL
3
CLEAR
4
DVCC
5
GND
6
SYNC/RSET
7
SCLK/OUTEN
8
SDIN/R0
24 DNC
23 DNC
22 GND
21 GND
20 DNC
19 DNC
18 IOUT
17 AVDD
9
AD
2
/R
1
0
AD
1
/R
2
1
AD
0
/R
3
1
2
R
EX
T
2
1
3
R
EX
T
1
4
V
R
EF
1
5
V
IN
1
6
G
N
D
3
2
NC
/I
F
AU
L
T
3
1
F
AU
LT
/T
EMP
3
0
R
ESET
2
9
H
W
SE
L
E
C
T
2
8
N
C
2
7
N
C
2
6
N
C
2
5
N
C
08923-
004
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PADDLE IS TIED TO GND.
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