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參數(shù)資料
| 型號： | AD5590BBCZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 32/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC I/O PORT-16 AMP 80-CSPBGA |
| 標準包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 12.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LFBGA，CSPBGA |
| 供應商設備封裝： | 80-CSP-BGA（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 16 個單端，單極 |
| 產(chǎn)品目錄頁面： | 777 (CN2011-ZH PDF) |
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AD5590
Rev. A | Page 38 of 44
Table 23. ADC Channel Selection
ADD3
ADD2
ADD1
ADD0
Analog Input Channel
0
VIN0
0
1
VIN1
0
1
0
VIN2
0
1
VIN3
0
1
0
VIN4
0
1
0
1
VIN5
0
1
0
VIN6
0
1
VIN7
1
0
VIN8
1
0
1
VIN9
1
0
1
0
VIN10
1
0
1
VIN11
1
0
VIN12
1
0
1
VIN13
1
0
VIN14
1
VIN15
Table 24. ADC Power Mode Selection
PM1
PM0
Mode
1
Normal operation. In this mode, the ADC remains in full power mode regardless of the status of any of the logic inputs. This
mode allows the fastest possible throughput rate from the ADC.
1
0
Full shutdown. In this mode, the ADC is in full shut down mode, with all circuitry on the ADC powered down. The ADC
retains the information in the control register while in full shutdown. The ADC remains in full shutdown until these bits are
changed in the control register.
0
1
Autoshutdown. In this mode, the ADC automatically enters shutdown mode at the end of each conversion when the control
register is updated. Wake-up time from shutdown is 1 s and the user should ensure that 1 s has elapsed before attempting
to perform a valid conversion on the ADC in this mode.
0
Autostandby. In this standby mode, portions of the ADC are powered down, but the on-chip bias generator remains
powered up. This mode is similar to autoshutdown and allows the ADC to power up within one dummy cycle, that is, 1 s
with a 20 MHz ASCLK.
ADC Sequencer Operation
The configuration of the SEQ and shadow bits in the control register allows the user to select a particular mode of operation of the
sequencer function. Table 25 outlines the four modes of operation of the sequencer.
Table 25. ADC Sequence Selection
SEQ
Shadow
Sequence Type
0
This configuration means the sequence function is not used. The analog input channel selected for each individual
conversion is determined by the contents of the channel address bits, ADD0 to ADD3, in each prior write operation. This
mode of operation reflects the normal operation of a multichannel ADC, without sequencer function being used, where
each write to the ADC selects the next channel for conversion (see Figure 69).
0
1
This configuration selects the shadow register for programming. After the write to the control register, the following
write operation loads the contents of the shadow register. This programs the sequence of channels to be converted on
continuously with each successive valid ASYNC falling edge (see the shadow register, Table 26, and Figure 70). The
channels selected need not be consecutive.
1
0
If the SEQ and shadow bits are set in this way, the sequence function is not interrupted upon completion of the write
operation. This allows other bits in the control register to be altered while in a sequence without terminating the cycle.
1
This configuration is used in conjunction with the channel address bits, ADD3 to ADD0, to program continuous
conversions on a consecutive sequence of channels from Channel 0 through to a selected final channel, as determined
by the channel address bits in the control register (see Figure 71).
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