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參數(shù)資料
型號： AD5590BBCZ
廠商： Analog Devices Inc
文件頁數(shù)： 28/44頁
文件大?。?/td> 0K
描述： IC ADC I/O PORT-16 AMP 80-CSPBGA
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 1M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 12.5mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 80-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 80-CSP-BGA（10x10）
包裝： 托盤
輸入數(shù)目和類型： 16 個單端，單極
產(chǎn)品目錄頁面： 777 (CN2011-ZH PDF)
AD5590
Rev. A | Page 34 of 44
ACCESSING THE ADC BLOCK
The ADC register can be accessed via the serial interface using
the ASCLK , ADIN, ADOUT, and ASYNC pins. The VDRIVE pin
can be used to dictate the logic levels of the output pins, allow-
ing the ADC to be interfaced to a 3 V DSP while the ADC is
operating at 5 V.
ADC Modes of Operation
The ADC has a number of different modes of operation. These
modes are designed to provide flexible power management options.
These options can be chosen to optimize the power dissipation/
throughput rate ratio for differing application requirements.
The mode of operation of the ADC is controlled by the power
management bits, PM1 and PM0, in the ADC control register,
as detailed in Table 21. When power supplies are first applied to
the ADC, ensure that the ADC is placed in the required mode
of operation (see the Powering Up the ADC section).
Normal Mode (PM1 = PM0 = 1)
This mode is intended for the fastest throughput rate perfor-
mance because the user does not have to worry about any
power-up times with the ADC remaining fully powered at all
times. Figure 64 shows the general diagram of the operation of
the ADC in this mode.
NOTES
1. CONTROL REGISTER DATA IS LOADED ON FIRST 12 SCLK CYCLES.
2. SHADOW REGISTER DATA IS LOADED ON FIRST 16 SCLK CYCLES.
ASYNC
ASCLK
1
16
12
CHANNE L IDENTIFIER BITS + CONVERSION RESULT
DATA IN TO CONTROL/SHADOW REGISTER
ADOUT
ADIN
07691-
064
Figure 64. ADC Normal Mode Operation
The conversion is initiated on the falling edge of ASYNC and
the track-and-hold enters hold mode as described in the Serial
Interface section. The data presented to the ADC on the ADIN
line during the first 12 clock cycles of the data transfer is loaded
to the ADC control register (provided the write bit is 1). If the
previous write had SEQ = 0 and shadow = 1, the data presented on
the ADIN line on the next 16 ASCLK cycles is loaded into the
shadow register. The ADC remains fully powered up in normal
mode at the end of the conversion as long as PM1 and PM0 are
set to 1 in the write transfer during that conversion. To ensure
continued operation in normal mode, PM1 and PM0 are both
loaded with 1 on every data transfer. Sixteen serial clock cycles
are required to complete the conversion and access the conver-
sion result. The track-and-hold returns to track on the 14th
ASCLK falling edge. ASYNC can then idle high until the next
conversion or can idle low until sometime prior to the next
conversion, (effectively idling ASYNC low).
When a data transfer is complete (ADOUT has returned to
three-state, weak/TRI bit = 0), another conversion can be
initiated by bringing ASYNC low again after the quiet time,
tQUIET, has elapsed.
Full Shutdown (PM1 = 1, PM0 = 0)
In this mode, all internal circuitry on the ADC is powered
down. The ADC retains information in the ADC control
register during full shutdown. The ADC remains in full
shutdown until the power management bits in the control
register, PM1 and PM0, are changed.
If a write to the ADC control register occurs while the ADC is
in full shutdown, with the power management bits changed to
PM0 = PM1 = 1, normal mode, the ADC begins to power up
on the ASYNC rising edge. The track-and-hold that was in hold
while the ADC was in full shutdown return to track on the 14th
ASCLK falling edge.
To ensure that the ADC is fully powered up, tPOWER-UP (t12)
should elapse before the next ASYNC falling edge. Figure 65
shows the general diagram for this sequence.
ASCLK
1
16
1
14
16
14
ADOUT
PART IS IN FULL
SHUTDOWN
PART BEGINS TO POWER UP ON ASYNC
RISING EDGE AS PM1 = 1, PM0 = 1
PART IS FULLY POWERED UP
ONCE TPOWER UP HAS ELAPSED
ADIN
ASYNC
t12
CHANNE L IDENTIFIER BITS + CONVERSION RESULT
DATA IN TO CONTROL REGISTER
CONTROL REGISTER IS LOADED ON THE
FIRST 12 CLOCKS, PM1 = 1, PM0 = 1
TO KEEP PART IN NORMAL MODE, LOAD
PM1 = 1, PM0 = 1 IN CONTROL REGISTER
DATA IN TO CONTROL/SHADOW REGISTER
07691-
065
Figure 65. Full Shutdown Mode Operation
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