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| 型號： | AD5560JSVUZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 30/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DPS PROGRAMABLE W/DAC 64TQFP |
| 設計資源： | Integrated Device Power Supply for PAD with Output Voltage Range 0 V to 25 V (CN0130) |
| 標準包裝： | 1,500 |
| 類型： | 電源 |
| 應用： | 自動測試設備 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-TQFP 裸露焊盤 |
| 供應商設備封裝： | 64-TQFP-EP（10x10） |
| 包裝： | 帶卷 (TR) |
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AD5560
Data Sheet
Rev. D | Page 36 of 68
FORCE AMPLIFIER STABILITY
There are three modes for configuring the force amplifier: safe
mode, autocompensation mode, and manual compensation mode.
Manual compensation mode has highest priority, followed by safe
mode, then autocompensation mode.
Safe Mode
Selected through Compensation Register 1 (see Table 20), this
mode guarantees stability of the force amplifier under all
conditions. Where the load is unknown, this mode is useful but
results in a slow response. This is the power-on default of the
AD5560.
Autocompensation Mode
Using this mode, the user inputs the CR and ESR values, and
the AD5560 decides the most appropriate compensation
scheme for these load conditions. The compensation chosen
is for an optimum tradeoff between ac response and stability.
Manual Compensation Mode
This mode allows access to all of the internal programmable
parameters to configure poles/zeros, which affect the dynamic
performance of the loop. These variables are outlined in
Figure 57 shows more details of the force amplifier block.
Table 12. External Variables
Name
Description
Min
Max
CR
DUT capacitance with contributing
ESR
10 nF
160 μF
RC
ESR in series with CR
1 mΩ
10 Ω
CD
DUT capacitance with negligible ESR
100 pF
10 nF
RD
Loading resistance at the DUT
~2 Ω
Infinity
IR
Current range
±5 μA
±1.2 A
Table 13. Internal Variables
Name
Description
Min
Max
RZ
Resistor in series with CC0, which
contributes a zero.
500 Ω
1.6 MΩ
RP
Resistor to 8 pF to contribute an
additional pole
200 Ω
1 MΩ
CC0:CC3
Capacitors to ensure
unconditional stability
100 pF
100 nF
CF0:CF4
Capacitors to optimize ac
performance into different CR, CD
4.7 nF
10 μF
gmx
Transconductance of force
amplifier input stage
40 μA/V
900 μA/V
DUTGND
FORCE
SENSE
VSENSE
–
+
×1
CF0
4.7nF
RZ:
500 TO
1.6M
CF1
22nF
CF2
100nF
CF3
470nF
CF4
2.2F
RSENSE 2
RSENSE 1
AD5560
FORCE VOLTAGE LOOP
EXTFORCE1
EXTFORCE2
100k
25k
20
200
2k
20k
100k
6k
100pF
330pF
3.3nF
CC0
CC1
CC2
CC3
FORCE
DAC
gm
RP:
200 TO 1M
8pF
AGND
+
–
+
–
CD
CR
RD
RC
07
77
9-
01
0
Figure 57. Block Diagram of a Force Amplifier Loop
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