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參數(shù)資料
| 型號： | AD5551BR |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/16頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 14BIT SERIAL-IN 8-SOIC |
| 產品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1 |
| 設置時間： | 1µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行 |
| 轉換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 6.05mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SOIC |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | 1M |
AD5551/AD5552
Rev. A | Page 14 of 16
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5551/AD5552 is via a
serial bus that uses standard protocol compatible with DSP
processors and microcontrollers. The communications channel
requires a 3-wire interface consisting of a clock signal, a data
signal and a synchronization signal. The AD5551/AD5552
require a 14-bit data word with data valid on the rising edge of
SCLK. The DAC update may be done automatically when all
the data is clocked in or it may be done under control of LDAC
(AD5552 only).
ADSP-21xx TO AD5551/AD5552 INTERFACE
Figure 25 shows a serial interface between the AD5551/AD5552
and the ADSP-21xx. The ADSP-21xx should be set to operate in
the SPORT (serial port) transmit alternate framing mode. The
ADSP-21xx is programmed through the SPORT control register
and should be configured as follows: internal clock operation,
active low framing, 16-bit word length. The first 2 bits are don’t
care as AD5551/AD5552 keeps the last 14 bits. Transmission is
initiated by writing a word to the Tx register after the SPORT
has been enabled. Because of the edges-triggered difference, an
inverter is required at the SCLKs between the DSP and the DAC.
DIN
SCLK
DT
SCLK
AD5551/
AD5552*
ADSP-21xx*
*ADDITIONAL PINS OMITTED FOR CLARITY.
**AD5552 ONLY.
CS
TFS
LDAC**
FO
019
43
-02
5
Figure 25. ADSP-21xx to AD5551/AD5552 Interface
68HC11 TO AD5551/AD5552 INTERFACE
Figure 26 shows a serial interface between the AD5551/AD5552
and the 68HC11 microcontroller. SCK of the 68HC11 drives the
SCLK of the DAC, while the MOSI output drives the serial data
line DIN. CS signal is driven from one of the port lines. The
68HC11 is configured for master mode; MSTR = 1, CPOL = 0,
and CPHA = 0. Data appearing on the MOSI output is valid on
the rising edge of SCK.
DIN
SCLK
MOSI
SCK
AD5551/
AD5552*
68HC11/
68L11*
*ADDITIONAL PINS OMITTED FOR CLARITY.
**AD5552 ONLY.
CS
PC7
LDAC**
PC6
01
94
3-
02
6
Figure 26. 68HC11/68L11 to AD5551/AD5552 Interface
MICROWIRE TO AD5551/AD5552 INTERFACE
Figure 27 shows an interface between the AD5551/AD5552 and
any MICROWIRE-compatible device. Serial data is shifted out
on the falling edge of the serial clock and into the AD5551/
AD5552 on the rising edge of the serial clock. No glue logic is
required as the DAC clocks data into the input shift register on
the rising edge.
DIN
SCLK
SO
SCLK
AD5551/
AD5552*
MICROWIRE*
*ADDITIONAL PINS OMITTED FOR CLARITY.
CS
0
19
43
-02
7
Figure 27. MICROWIRE to AD5551/AD5552 Interface
80C51/80L51 TO AD5551/AD5552 INTERFACE
A serial interface between the AD5551/AD5552 and the 80C51/
80L51 microcontroller is shown in Figure 28. TxD of the micro-
controller drives the SCLK of the AD5551/AD5552, while RxD
drives the serial data line of the DAC. P3.3 is a bit programmable
pin on the serial port which is used to drive CS.
DIN
SCLK
RxD
TxD
AD5551/
AD5552*
80C51/
80L51*
*ADDITIONAL PINS OMITTED FOR CLARITY.
**AD5552 ONLY.
CS
P3.3
LDAC**
P3.4
01
94
3-
0
28
Figure 28. 80C51/80L51 to AD5551/AD5552 Interface
The 80C51/80L51 provides the LSB first, while the AD5551/
AD5552 expect the MSB of the 14-bit word first. Take care to
ensure that the transmit routine takes this into account. Usually
it can be done through software by shifting out and accumu-
lating the bits in the correct order before inputting to the DAC.
Also, 80C51 outputs 2 byte words/16 bits data, thus the first
two bits, after rearrangement, should be don’t care as they are
dropped from the 14-bit word of the DAC.
When data is to be transmitted to the DAC, P3.3 is taken low.
Data on RxD is valid on the falling edge of TxD, so the clock must
be inverted as the DAC clocks data into the input shift register
on the rising edge of the serial clock. The 80C51/80L51 transmits
its data in 8-bit bytes with only eight falling clock edges occur-
ring in the transmit cycle. As the DAC requires a 14-bit word,
P3.3 (or any one of the other programmable bits) is the CS
input signal to the DAC, so P3.3 should be brought low at the
beginning of the 16-bit write cycle 2 × 8 bit words and held low
until the 16-bit 2 × 8 cycle is completed. After that, P3.3 is
brought high again and the new data loads to the DAC. Again,
the first two bits, after rearranging, should be don’t care. LDAC
on the AD5552 may also be controlled by the 80C51/80L51
serial port output by using another bit programmable pin, P3.4.
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