VIN DAC ACQUISITION CIRCUIT VOUT
參數(shù)資料
型號(hào)： AD5532BBCZ-1
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 4/16頁(yè)
文件大?。?/td> 0K
描述： IC DAC 14BIT 32CH BIPO 74-CSPBGA
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 1
設(shè)置時(shí)間： 22µs
位數(shù)： 14
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 34
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 623mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 74-LBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 74-CSPBGA（12x12）
包裝： 托盤
輸出數(shù)目和類型： 32 電壓，單極
采樣率（每秒）： 45k
配用： EVAL-AD5532HSEBZ-ND - BOARD EVAL FOR AD5532HS
EVAL-AD5532EBZ-ND - BOARD EVAL FOR AD5532
REV. A
AD5532B
–12–
TRACK
VIN
DAC
ACQUISITION
CIRCUIT
VOUT1
BUSY
OUTPUT
STAGE
CONTROLLER
THRESHOLD
VOLTAGE
PIN
DRIVER
DEVICE
UNDER
TEST
ONLY ONE CHANNEL SHOWN FOR SIMPLICITY
AD5532B
Figure 9. Typical ATE Circuit Using
TRACK Input
of the pin driver, the comparator output switches. The
C/P
then knows what code is required to be input in order to obtain
the desired voltage at the DUT. The
TRACK input is now
brought high and the part begins to acquire VIN. At this stage,
BUSY goes low until V
IN has been acquired. The output buffer
is then switched from VIN to the output of the DAC.
MODES OF OPERATION
The AD5532B can be used in four different modes of oper-
ation. These modes are set by two mode bits, the first two bits in
the serial word.
OFFSET SEL
A4 –A0
CAL
0
MSB
MODE BITS
0
TEST BIT
LSB
MODE BIT 1 MODE BIT 2
a. 10-Bit Input Serial Write Word (ISHA Mode)
OFFSET SEL
A4 –A0
CAL
1
0
MSB
MODE BITS
0
TEST BIT
LSB
DB13–DB0
b. 24-Bit Input Serial Write Word (DAC Mode)
OFFSET SEL
A4 –A0
CAL
0
1
MSB
LSB
MODE BITS
DB1 3 –DB0
0
TEST BIT
10-BIT
SERIAL WORD
WRITTEN TO PART
14-BIT DATA
READ FROM PART AFTER
NEXT FALLING EDGE OF
SYNC
(DB13 = MSB OF DAC WORD)
MSB
LSB
c. Input Serial Interface (Acquire and Readback Mode)
OFFSET SEL
A4 –A0
CAL
1
MSB
LSB
MODE BITS
DB1 3 –DB0
0
TEST BIT
10-BIT
SERIAL WORD
WRITTEN TO PART
14-BIT DATA
READ FROM PART AFTER
NEXT FALLING EDGE OF
SYNC
(DB13 = MSB OF DAC WORD)
MSB
LSB
d. Input Serial Interface (Readback Mode)
Figure 10. Serial Interface Formats
Table II. Modes of Operation
Mode Bit 1
Mode Bit 2
Operating Mode
00
ISHA Mode
01
DAC Mode
10
Acquire and Readback
11
Readback
1. ISHA Mode
In this mode, a channel is addressed and that channel
acquires the voltage on VIN. This mode requires a 10-bit
write (see Figure 3) to address the relevant channel (VOUT0–
VOUT31, offset channel or all channels). MSB is written first.
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參數(shù)描述
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