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參數(shù)資料
| 型號(hào)： | AD5532BBCZ-1 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT 32CH BIPO 74-CSPBGA |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時(shí)間： | 22µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 34 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 623mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 74-LBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 74-CSPBGA（12x12） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 32 電壓，單極 |
| 采樣率（每秒）： | 45k |
| 配用： | EVAL-AD5532HSEBZ-ND - BOARD EVAL FOR AD5532HS EVAL-AD5532EBZ-ND - BOARD EVAL FOR AD5532 |
REV. A
AD5532B
–9–
TERMINOLOGY
DAC MODE
Integral Nonlinearity (INL)
This is a measure of the maximum deviation from a straight line
passing through the endpoints of the DAC transfer function. It is
expressed as a percentage of full-scale span.
Differential Nonlinearity (DNL)
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified DNL of
±1 LSB maximum ensures
monotonicity.
Offset
Offset is a measure of the output with all zeros loaded to the
DAC and OFFS_IN = 0. Since each DAC is lifted off the ground
by approximately 50 mV, this output will typically be:
V
GAIN
mV
OUT
=× 50
Full-Scale Error
This is a measure of the output error with all 1s loaded to the
DAC. It is expressed as a percentage of full-scale range. It includes
the offset error. See Figure 6. It is calculated as:
Full Scale Error
V
Ideal Gain
REFIN
OUT Full Scale
-
=×
()
() –
where
Ideal Gain
3.52 for AD5532B
1
=
Output Settling Time
This is the time taken from when the last data bit is clocked into
the DAC until the output has settled to within
±0.39%.
OFFS_IN Settling Time
This is the time taken from a 0 V–3 V step change in input voltage
on OFFS_IN until the output has settled to within
±0.39%.
Digital-to-Analog Glitch Impulse
This is the area of the glitch injected into the analog output when
the code in the DAC register changes state. It is specified as the
area of the glitch in nV-secs when the digital code is changed by
1 LSB at the major carry transition (011 ...11 to 100 . . . 00 or
100 . . . 00 to 011 . . . 11).
Digital Crosstalk
This is the glitch impulse transferred to the output of one DAC at
midscale while a full-scale code change (all 1s to all 0s and vice
versa) is being written to another DAC. It is expressed in nV-secs.
Analog Crosstalk
This the area of the glitch transferred to the output (VOUT) of
one DAC due to a full-scale change in the output (VOUT) of
another DAC. The area of the glitch is expressed in nV-secs.
Digital Feedthrough
This is a measure of the impulse injected into the analog outputs
from the digital control inputs when the part is not being written
to, i.e.,
CS/SYNC is high. It is specified in nV-secs and is mea-
sured with a worst-case change on the digital input pins, e.g., from
all 0s to all 1s and vice versa.
Output Noise Spectral Density
This is a measure of internally generated random noise. Random
noise is characterized as a spectral density (voltage per root Hertz).
It is measured by loading all DACs to midscale and measuring
noise at the output. It is measured in nV/
√Hz.
Output Temperature Coefficient
This is a measure of the change in analog output with changes
in temperature. It is expressed in ppm/
°C.
DC Power Supply Rejection Ratio
DC power supply rejection ratio (PSRR) is a measure of the change
in analog output for a change in supply voltage (VDD and VSS).
It is expressed in dBs. VDD and VSS are varied
±5%.
DC Crosstalk
This is the change in the output level of one DAC at midscale in
response to a full-scale code change (all 0s to all 1s and vice versa)
and output change of all other DACs. It is expressed in
V.
ISHA MODE
Total Unadjusted Error (TUE)
This is a comprehensive specification that includes relative
accuracy, gain and offset errors. It is measured by sampling a
range of voltages on VIN and comparing the measured voltages
on VOUT to the ideal value. It is expressed in mV.
VIN to VOUT Nonlinearity
This is a measure of the maximum deviation from a straight line
passing through the endpoints of the VIN versus VOUT transfer
function. It is expressed as a percentage of the full-scale span.
Offset Error
This is a measure of the output error when VIN = 70 mV. Ideally,
with VIN = 70 mV:
V
Gain
V
mV
OUT
OFFS
IN
=×
() (
) ×
[]
70
1
––
_
Offset error is a measure of the difference between VOUT (actual)
and VOUT (ideal). It is expressed in mV and can be positive or
negative. See Figure 7.
Gain Error
This is a measure of the span error of the analog channel. It is
the deviation in slope of the transfer function expressed in mV.
See Figure 7. It is calculated as:
Gain Error = Actual Full-Scale Output –
Ideal Full-Scale Output – Offset Error
where
Ideal Full-Scale Output = (Gain
2.96) – [(Gain – 1)
VOFFS_IN]
AC Crosstalk
This is the area of the glitch that occurs on the output of one
channel while another channel is acquiring. It is expressed in
nV-secs.
Output Settling Time
This is the time taken from when
BUSY goes high to when the
output has settled to
±0.018%.
Acquisition Time
This is the time taken for the VIN input to be acquired. It is the
length of time that
BUSY stays low.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD5532HS | 制造商:AD 制造商全稱:Analog Devices 功能描述:32-Channel 14-Bit DAC with High-Speed 3-Wire Serial Interface |
| AD5532HSABC | 功能描述:IC DAC 14BIT 32CH 74-CSPBGA RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 設(shè)置時(shí)間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD5532HSABCZ | 功能描述:IC DAC 14BIT 32CH HS 74-CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 設(shè)置時(shí)間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD5533 | 制造商:AD 制造商全稱:Analog Devices 功能描述:32-Channel Infinite Sample-and-Hold |
| AD5533ABC-1 | 制造商:Analog Devices 功能描述:Sample and Hold 32-CH 16us 74-Pin CSP-BGA |
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