參數(shù)資料
型號(hào)： AD5522JSVDZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 52/64頁(yè)
文件大?。?/td> 0K
描述： IC PMU QUAD 16BIT DAC 80-TQFP
產(chǎn)品變化通告： Improve FI ac crosstalk
設(shè)計(jì)資源： Parametric Measurement Unit and Supporting Components for PAD Appls Using AD5522 and AD7685 (CN0104)
標(biāo)準(zhǔn)包裝： 1
類型： 每引腳參數(shù)測(cè)量單元（PPMU）
應(yīng)用： 自動(dòng)測(cè)試設(shè)備
安裝類型： 表面貼裝
封裝/外殼： 80-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 80-TQFP（12x12）
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 798 (CN2011-ZH PDF)
AD5522
Data Sheet
Rev. E | Page 56 of 64
READBACK OF COMPARATOR STATUS REGISTER
The comparator status register is a read-only register that
provides access to the output status of each comparator pin on
the chip. Table 33 shows the format of the comparator register
readback word.
READBACK OF ALARM STATUS REGISTER
The alarm status register is a read-only register that provides
information about temperature, clamp, and guard alarm events
(see Table 34). Temperature alarm status is also available in any
of the four PMU readback registers.
Table 33. Comparator Status Register (Read-Only)
Bit
Bit Name
Description
23 (MSB)
MODE1
0
22
MODE0
1
Comparator Status Register-Specific Bits
21
CPOL0
Comparator output conditions per channel corresponding to the comparator output pins.
1 = PMU comparator output is high.
0 = PMU comparator output is low.
20
CPOH0
19
CPOL1
18
CPOH1
17
CPOL2
16
CPOH2
15
CPOL3
14
CPOH3
13 to 0 (LSB)
Unused
readback bits
Loads with zeros.
Table 34. Alarm Status Register Readback
Bit
Bit Name
Description
23
(MSB)
MODE1
1
22
MODE0
1
Alarm Status Register-Specific Bits
21
LTMPALM
TMPALM corresponds to the open-drain TMPALM output pin that flags a temperature event exceeding the default
or user programmed level. The temperature alarm is a per-device alarm; the latched (LTMPALM) and unlatched
(TMPALM) bits indicate whether a temperature event occurred and whether the alarm still exists (that is, whether
the junction temperature still exceeds the programmed alarm level). To reset an alarm event, the user must write a
1 to the clear bit (Bit 6)
in the PMU register.
20
TMPALM
19
LG0
LGx is the per-channel latched guard alarm bit, and Gx is the unlatched guard alarm bit. These bits indicate which
channel flagged the alarm on the open-drain alarm pin, CGALM, and whether the alarm condition still exists.
18
G0
17
LG1
16
G1
15
LG2
14
G2
13
LG3
12
G3
11
LC0
LCx is the per-channel latched clamp alarm bit, and Cx is the unlatched clamp alarm bit. These bits indicate which
channel flagged the alarm on the open-drain alarm pin CGALM and whether the alarm condition still exists.
10
C0
9
LC1
8
C1
7
LC2
6
C2
5
LC3
4
C3
3 to 0
(LSB)
Unused
readback
bits
Loads with 0s.
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