參數(shù)資料
型號(hào): AD5422BREZ-REEL
廠商: Analog Devices Inc
文件頁(yè)數(shù): 26/44頁(yè)
文件大?。?/td> 0K
描述: IC DAC 16BIT 1CH SRL INP 24TSSOP
產(chǎn)品培訓(xùn)模塊: Power Line Monitoring
Data Converter Fundamentals
DAC Architectures
設(shè)計(jì)資源: 16-Bit Fully Isolated Output Module Using AD5422 and ADuM1401 (CN0065)
Simplified 16-Bit Voltage Output and 4 mA-to-20 mA Output Solution Using AD5422 (CN0077)
標(biāo)準(zhǔn)包裝: 2,500
設(shè)置時(shí)間: 25µs
位數(shù): 16
數(shù)據(jù)接口: MICROWIRE?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字,雙 ±
功率耗散(最大): 950mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm)裸露焊盤
供應(yīng)商設(shè)備封裝: 24-TSSOP 裸露焊盤
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 1 電流,單極;1 電流,雙極;1 電壓,單極;1 電壓,雙極
采樣率(每秒): 40k
AD5412/AD5422
Data Sheet
Rev. I | Page 32 of 44
RESET REGISTER
The reset register is addressed by setting the address word of the input shift register to 0x56. The data to be written to the reset register is
entered in the D0 position as shown in Table 17. The reset register options are shown in Table 17 and Table 18.
Table 17. Programming the Reset Register
MSB
LSB
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
Reset
Table 18. Reset Register Functions
Option
Description
Reset
Setting this bit performs a reset operation, restoring the AD5412/AD5422 to its power-on state.
STATUS REGISTER
The status register is a read-only register. The status register functionality is shown in Table 19 and Table 20.
Table 19. Decoding the Status Register
MSB
LSB
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
IOUT fault
Slew active
Over temp
Table 20. Status Register Functions
Option
Description
IOUT Fault
This bit is set if a fault is detected on the IOUT pin.
Slew Active
This bit is set while the output value is slewing (slew rate control enabled).
Over Temp
This bit is set if the AD5412/AD5422 core temperature exceeds ~150°C.
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