參數(shù)資料
型號(hào)： AD5422BCPZ-REEL
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： SERIAL INPUT LOADING, 32 us SETTLING TIME, 16-BIT DAC, QCC40
封裝： 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD-2, LFCSP-40
文件頁(yè)數(shù)： 26/40頁(yè)
文件大?。?/td> 1323K
代理商： AD5422BCPZ-REEL
AD5412/AD5422
Rev. C | Page 32 of 40
DIGITAL POWER SUPPLY
By default, the DVCC pin accepts a power supply of 2.7 V to
5.5 V. Alternatively, via the DVCC SELECT pin, an internal 4.5 V
power supply can be output on the DVCC pin for use as a digital
power supply for other devices in the system or as a termination
for pull-up resistors. This facility offers the advantage of not
having to bring a digital supply across an isolation barrier. The
internal power supply is enabled by leaving the DVCC SELECT
pin unconnected. To disable the internal supply, tie DVCC
SELECT to 0 V. DVCC is capable of supplying up to 5 mA of
current (for a load regulation graph, see Figure 10).
EXTERNAL BOOST FUNCTION
The addition of an external boost transistor, as shown in
Figure 67, reduces the power dissipated in the AD5412/AD5422
by reducing the current flowing in the on-chip output transistor
(dividing it by the current gain of the external circuit). A
discrete NPN transistor with a breakdown voltage, BVCEO,
greater than 40 V can be used. The external boost capability
has been developed for users who may wish to use the
AD5412/AD5422 at the extremes of the supply voltage, load
current, and temperature range. The boost transistor can also
be used to reduce the amount of temperature-induced drift in
the part. This minimizes the temperature-induced drift of the
on-chip voltage reference, which improves on drift and
linearity.
BOOST
MJD31C
OR
PBSS8110Z
RLOAD
0.022F
1k
AD5412/
AD5422
IOUT
06
99
6-
06
1
Figure 67. External Boost Configuration
EXTERNAL COMPENSATION CAPACITOR
The voltage output can ordinarily drive capacitive loads of up to
20 nF; if there is a requirement to drive greater capacitive loads,
of up to 1 μF, an external compensation capacitor can be con-
nected between the CCOMP and VOUT pins. The addition of the
capacitor keeps the output voltage stable but also reduces the
bandwidth and increases the settling time of the voltage output.
DIGITAL SLEW RATE CONTROL
The slew rate control feature of the AD5412/AD5422 allows the
user to control the rate at which the output voltage or current
changes. With the slew rate control feature disabled, the output
changes at a rate limited by the output drive circuitry and the
attached load. See Figure 62 for current output step and
Figure 36 for voltage output step. To reduce the slew rate, enable
the slew rate control feature. With the feature enabled via the
SREN bit of the control register (see Table 14), the output, instead
of slewing directly between two values, steps digitally at a rate
defined by two parameters accessible via the control register, as
shown in Table 14. The parameters are set by the SR clock and
SR step bits. SR clock defines the rate at which the digital slew is
updated; SR step defines by how much the output value changes
at each update. Both parameters together define the rate of
change of the output voltage or current. Table 22 and Table 23
outline the range of values for both the SR clock and SR step
parameters. Figure 68 shows the output current changing for
ramp times of 10 ms, 50 ms, and 100 ms.
Table 22. Slew Rate Step Size Options
SR Step
AD5412 Step Size
(LSB)
AD5422 Step
Size (LSB)
000
1/16
1
001
1/8
2
010
1/4
4
011
1/2
8
100
1
16
101
2
32
110
4
64
111
8
128
Table 23. Slew Rate Update Clock Options
SR Clock
Update Clock Frequency (Hz)
0000
257,730
0001
198,410
0010
152,440
0011
131,580
0100
115,740
0101
69,440
0110
37,590
0111
25,770
1000
20,160
1001
16,030
1010
10,290
1011
8280
1100
6900
1101
5530
1110
4240
1111
3300
The time it takes for the output to slew over a given output
range can be expressed as follows:
Size
LSB
Frequency
Clock
Update
Size
Step
Change
Output
Time
Slew
×
=
(1)
where:
Slew Time is expressed in seconds.
Output Change is expressed in amps for IOUT or volts for VOUT.
When the slew rate control feature is enabled, all output
changes change at the programmed slew rate; if the CLEAR
pin is asserted, the output slews to the zero-scale value at the
programmed slew rate. The output can be halted at its current
value with a write to the control register. To avoid halting the
output slew, the slew active bit (see Table 19) can be read to
check that the slew has completed before writing to any of the
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