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參數(shù)資料
| 型號： | AD5380BSTZ-3 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 25/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT 40CHAN 3V 100LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 產(chǎn)品變化通告： | Redesign Change 28/Oct/2011 |
| 設(shè)計資源： | 40 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5380 (CN0007) Output Channel Monitoring Using AD5380 (CN0008) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時間： | 6µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | I²C，并聯(lián)，串行 |
| 轉(zhuǎn)換器數(shù)目： | 40 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 125mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 40 電壓，單極 |
| 采樣率（每秒）： | 125k |
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Data Sheet
AD5380
Rev. C | Page 31 of 40
MICROPROCESSOR INTERFACING
Parallel Interface
The AD5380 can be interfaced to a variety of 16-bit microcon-
trollers or DSP processors. Figure 35 shows the AD5380 family
interfaced to a generic 16-bit microcontroller/DSP processor.
The lower address lines from the processor are connected to
A0 to A5 on the AD5380. The upper address lines are decoded
to provide a CS, LDAC signal for the AD5380. The fast interface
timing of the AD5380 allows direct interface to a wide variety
of microcontrollers and DSPs, as shown in Figure 35.
AD5380 to MC68HC11
The serial peripheral interface (SPI) on the MC68HC11 is
configured for Master mode (MSTR = 1), Clock Polarity bit
(CPOL) = 0, and the Clock Phase bit (CPHA) = 1. The SPI is
configured by writing to the SPI control register (SPCR)—see
the 68HC11 User Manual. SCK of the 68HC11 drives the SCLK
of the AD5380, the MOSI output drives the serial data line
(DIN) of the AD5380, and the MISO input is driven from SDO.
The SYNC signal is derived from a port line (PC7).
When data is being transmitted to the AD5380, the SYNC line
is taken low (PC7). Data appearing on the MOSI output is valid
on the falling edge of SCK. Serial data from the 68HC11 is
transmitted in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle.
03731-034
MC68HC11
AD5380
MISO
MOSI
SCK
PC7
SDO
RESET
SER/PAR
DIN
SCLK
SYNC
SPI/I2C
DVDD
Figure 34. AD5380-to-MC68HC11 Interface
03731-035
CONTROLLER/
DSP PROCESSOR1
AD5380
ADDRESS
DECODE
UPPER BITS OF
ADDRESS BUS
DATA
BUS
A5
D15
D0
A4
A3
A2
A1
A0
R/W
A5
A4
A3
A2
A1
A0
WR
REG1
REG0
D13
D0
CS
LDAC
1ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 35. AD5380-to-Parallel Interface
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| AD5381BST-5-REEL | 制造商:Analog Devices 功能描述:DAC 40-CH Resistor-String 12-bit 100-Pin LQFP T/R |
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