參數(shù)資料
型號: AD5306ARU
廠商: Analog Devices Inc
文件頁數(shù): 9/24頁
文件大?。?/td> 0K
描述: IC DAC 8BIT QUAD W/BUFF 16-TSSOP
產(chǎn)品培訓模塊: Data Converter Fundamentals
DAC Architectures
標準包裝: 96
設(shè)置時間: 6µs
位數(shù): 8
數(shù)據(jù)接口: I²C,串行
轉(zhuǎn)換器數(shù)目: 4
電壓電源: 單電源
功率耗散(最大): 4.5mW
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 管件
輸出數(shù)目和類型: 4 電壓,單極;4 電壓,雙極
采樣率(每秒): 167k
AD5306/AD5316/AD5326
Rev. F | Page 17 of 24
DEFAULT READBACK CONDITIONS
All pointer byte bits power up to 0. Therefore, if the user
initiates a readback without first writing to the pointer byte, no
single DAC channel has been specified. In this case, the default
readback bits are all 0 except for the CLR bit and the PD bit,
which are 1.
MULTIPLE DAC WRITE SEQUENCE
Because there are individual bits in the pointer byte for each DAC,
it is possible to write the same data and control bits to two, three,
or four DACs simultaneously by setting the relevant bits to 1.
MULTIPLE DAC READBACK SEQUENCE
If the user attempts to read back data from more than one DAC
at a time, the part reads back the power-on condition of GAIN,
BUF, and data bits (all 0), and the current state of CLR and PD.
02066-032
BUF
CLR
PD
D7
D6
D5
D4
GAIN
LSB
MSB
8-BIT AD5306
CLR
D9
D8
D7
D6
D11
D10
D9
D8
MOST SIGNIFICANT DATA BYTE
LSB
MSB
10-BIT AD5316
LSB
MSB
12-BIT AD5326
CLR
LEAST SIGNIFICANT DATA BYTE
D3
D2
D1
D0
0
D5
D4
D3
D2
D1
D0
0
D7
D6
D5
D4
D3
D2
D1
D0
LSB
MSB
8-BIT AD5306
LSB
MSB
10-BIT AD5316
LSB
MSB
12-BIT AD5326
00
0
BUF
PD
GAIN
BUF
PD
GAIN
Figure 32. Data Formats for Write and Readback
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