參數(shù)資料
型號(hào)： AD5306ARU
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 10/24頁(yè)
文件大小： 0K
描述： IC DAC 8BIT QUAD W/BUFF 16-TSSOP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 96
設(shè)置時(shí)間： 6µs
位數(shù)： 8
數(shù)據(jù)接口： I²C，串行
轉(zhuǎn)換器數(shù)目： 4
電壓電源： 單電源
功率耗散（最大）： 4.5mW
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 16-TSSOP
包裝： 管件
輸出數(shù)目和類型： 4 電壓，單極；4 電壓，雙極
采樣率（每秒）： 167k
AD5306/AD5316/AD5326
Rev. F | Page 18 of 24
WRITE OPERATION
When writing to the AD5306/AD5316/AD5326 DACs, the user
must begin with an address byte (R/W = 0), after which the DAC
acknowledges that it is prepared to receive data by pulling SDA
low. This address byte is followed by the pointer byte, which is
also acknowledged by the DAC. Two bytes of data are then
written to the DAC, as shown in Figure 33. A stop condition
follows.
READ OPERATION
When reading data back from the AD5306/AD5316/AD5326
DACs, the user begins with an address byte (R/W = 0), after
which the DAC acknowledges that it is prepared to receive data
by pulling SDA low. This address byte is usually followed by the
pointer byte, which is also acknowledged by the DAC. Following
this, there is a repeated start condition by the master, and the
address is resent with R/W = 1. This is acknowledged by the
DAC, indicating that it is prepared to transmit data. Two bytes
of data are then read from the DAC, as shown in Figure 34. A
stop condition follows.
A1
X
LSB
X
R/W
A0
0
LEAST SIGNIFICANT DATA BYTE
MOST SIGNIFICANT DATA BYTE
00
1
ACK
BY
AD53x6
ACK
BY
AD53x6
ACK
BY
AD53x6
ACK
BY
AD533x
MSB
ADDRESS BYTE
POINTER BYTE
START
CONDITION
BY
MASTER
STOP
CONDITION
BY
MASTER
SCL
SDA
SCL
SDA
MSB
LSB
MSB
LSB
02066-033
Figure 33. Write Sequence
02066-034
DATA BYTE
LEAST SIGNIFICANT DATA BYTE
SCL
SDA
MSB
SCL
SDA
MSB
ADDRESS BYTE
SCL
SDA
MSB
LSB
POINTER BYTE
ADDRESS BYTE
LSB
ACK
BY
AD53x6
ACK
BY
AD53x6
ACK
BY
AD53x6
ACK
BY
MASTER
START
CONDITION
BY
MASTER
REPEATED
START
CONDITION
BY
MASTER
NO
ACK
BY
MASTER
STOP
CONDITION
BY
MASTER
X
R/W
0
00
1
A1
R/W
A0
A1
A0
00
0
1
LSB
Figure 34. Readback Sequence
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