
AD5302/AD5312/AD5322
Rev. D | Page 12 of 24
600
400
300
100
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
00
92
8-
0
18
I DD
(
A
)
200
500
VDD(V)
BOTH DACS IN GAIN-OF-TWO MODE
REFERENCE INPUTS BUFFERED
+105°C
+25°C
–40°C
Figure 18. Supply Current vs. Supply Voltage
0.8
0.6
0.2
0
2.7
3.2
3.7
4.2
4.7
5.2
00
92
8-
0
19
I DD
(A
)
0.4
1.0
VDD (V)
+105°C
+25°C
–40°C
BOTH DACS IN
THREE-STATE CONDITION
Figure 19. Power-Down Current vs. Supply Voltage
500
400
200
100
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
00
92
8-
0
20
I DD
(A
)
300
700
VLOGIC (V)
TA = 25°C
VDD = 5V
VDD = 3V
600
Figure 20. Supply vs. Logic Input Voltage
CH2
CH1 1V, CH2 5V, TIME BASE = 5s/DIV
00
92
8-
0
21
CH1
VDD = 5V
TA = 25°C
CLK
VOUT
Figure 21. Half-Scale Setting ( to Scale Code Change)
CH2
CH1 1V, CH2 1V, TIME BASE = 20s/DIV
00
92
8-
0
22
CH1
VOUTA
TA = 25°C
VDD
Figure 22. Power-On Reset to 0 V
CH3
CH1 1V, CH3 5V, TIME BASE = 1s/DIV
00
92
8-
0
23
CH1
TA = 25°C
VOUT
CLK
Figure 23. Existing Power-Down to Midscale