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參數(shù)資料
| 型號(hào)： | AD5301BRTZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 8/24頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8BIT 2WIRE I2C SOT23-6 |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 設(shè)置時(shí)間： | 6µs |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 1.4mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-6 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-6 |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | 167k |
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AD5301/AD5311/AD5321
Rev. B | Page 16 of 24
READ OPERATION
When reading data back from the AD5301/AD5311/AD5321
DACs, the user must begin with an address byte after which
the DAC acknowledges that it is prepared to transmit data by
pulling SDA low. There are two different read operations. In the
case of the AD5301, the readback is a single byte that consists of
the eight data bits in the DAC register. However, in the case
of the AD5311 and AD5321, the readback consists of two bytes
that contain both the data and the power-down mode bits. The
read operations for the three DACs are shown in Figure 32 to
SCL
SDA
ACK
BY
AD5301
NO ACK
BY
MASTER
START
COND
BY
MASTER
*THIS BIT MUST BE 0 IN THE 6-LEAD SOT-23 VERSION.
ADDRESS BYTE
00
0
1
A1*
A0
R/W
STOP
COND
BY
MASTER
DATA BYTE
D7
D6
D5
D4
D3
D2
D1
D0
009
27
-030
Figure 32. AD5301 Readback Sequence
SCL
SDA
SCL
SDA
LEAST SIGNIFICANT CONTROL BYTE
*THIS BIT MUST BE 0 IN THE 6-LEAD SOT-23 VERSION.
NO ACK
BY
MASTER
STOP
COND
BY
MASTER
PD1
X
PD0
D9
D8
D7
D6
0A1*
A0
00
11
R/W
D5
D4
D3
D2
D1
D0
X
ACK
BY
AD5311
ACK
BY
AD5311
START
COND
BY
MASTER
MOST SIGNIFICANT BYTE
ADDRESS BYTE
00
92
7-
0
31
Figure 33. AD5311 Readback Sequence
LEAST SIGNIFICANT BYTE
SCL
SDA
SCL
SDA
ACK
BY
AD5321
NO ACK
BY
MASTER
START
COND
BY
MASTER
STOP
COND
BY
MASTER
*THIS BIT MUST BE 0 IN THE 6-LEAD SOT-23 VERSION.
ADDRESS BYTE
STOP
COND
BY
MASTER
MOST SIIGNIFICANT BYTE
0
D7
D6
D5
D4
D3
D2
D1
D0
00
1
A1*
A0
R/W
X
PD1
PD0
D11
D10
D9
D8
00
92
7-
03
2
Figure 34. AD5321 Readback Sequence
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD5301BRTZ-REEL71 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2.5 V to 5.5 V, 120 ??A, 2-Wire Interface, Voltage-Output 8-/10-/12-Bit DACs |
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| AD5302_11 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2.5 V to 5.5 V, 230 ??A, Dual Rail-to-Rail, Voltage Output 8-/10-/12-Bit DACs |
| AD53020 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Four Channel ECL Delay Line |
| AD53020JP | 制造商:Analog Devices 功能描述: |
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