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參數(shù)資料
| 型號： | AD5273BRJZ50-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC POT DGTL 50K 64POS SOT23 |
| 標準包裝： | 1 |
| 接片： | 64 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標準值 300 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-8 |
| 包裝： | 標準包裝 |
| 其它名稱： | AD5273BRJZ50-REEL7DKR |
AD5273
Rev. H | Page 15 of 24
Unlike rheostat mode where the absolute tolerance is high,
potentiometer mode yields an almost ratiometric function of
D/63 with a relatively small error contributed by the RW terms.
Therefore, the tolerance effect is almost cancelled. Although the
step resistor, RS, and CMOS switch resistor, RW, have very differ-
ent temperature coefficients, the ratiometric adjustment also
reduces the overall temperature coefficient effect to 5 ppm/°C,
except at low value codes where RW dominates.
Potentiometer mode includes op amp feedback resistor networks
and other voltage scaling applications. Terminal A, Terminal W,
and Terminal B can in fact be input or output terminals, provided
that |VAB|, |VWA|, and |VWB| do not exceed VDD to GND.
ESD PROTECTION
Digital inputs SDA and SCL are protected with a series input
resistor and parallel Zener ESD structures (see Figure 36).
LOGIC
340
Ω
03224-035
Figure 36. ESD Protection of Digital Pins
TERMINAL VOLTAGE OPERATING RANGE
There are also ESD protection diodes between VDD and the
RDAC terminals. The VDD of AD5273 therefore defines their
voltage boundary conditions (see Figure 37). Supply signals
present on Terminal A, Terminal B, and Terminal W that exceed
VDD are clamped by the internal forward-biased diodes.
GND
A
W
B
VDD
03224-036
Figure 37. Maximum Terminal Voltages Set by VDD
POWER-UP/POWER-DOWN SEQUENCES
Because of the ESD protection diodes, it is important to power
VDD first before applying any voltages to Terminal A, Terminal B,
and Terminal W. Otherwise, the diode is forward-biased such that
VDD is powered unintentionally and can affect the rest of the user’s
circuits. The ideal power-up sequence is in the following order:
GND, VDD, digital inputs, and VA/VB/VW. The order of powering
VA, VB, VW, and digital inputs is not important as long as they are
powered after VDD. Similarly, VDD should be powered down last.
POWER SUPPLY CONSIDERATIONS
To minimize the package pin count, both OTP and normal opera-
ting voltage supplies are applied to the same VDD terminal of the
AD5273. The AD5273 employs fuse link technology that requires
from 5 V to 5.5 V for the 1 kΩ (DD8) and 10 kΩ (DD9) options,
or from 4.75 V to 5.25 V for the 50 kΩ (DYG) and 100 kΩ (DYH)
options, for blowing the internal fuses to achieve a given setting,
but normal VDD can be in the range of 2.7 V to 5.5 V after
completing the fuse programming process. As a result, dual
voltage supplies and isolation are needed if the system VDD is
outside the required VDD_OTP range. For successful OTP, the fuse
programming supply (either an on-board regulator or rack-mount
power supply) must be rated at 5 V to 5.5 V for the 1 kΩ (DD8)
and 10 kΩ (DD9) options, or at 4.75 V to 5.25 V for the 50 kΩ (DYG)
and 100 kΩ (DYH) options, and be capable of sourcing 100 mA
for 400 ms. When fuse programming is completed, the VDD_OTP
supply can be removed to allow normal operation of 2.7 V to 5.5 V;
the device then reduces the current consumption to the μA range.
When operating systems at 2.7 V, use of the bidirectional low
threshold P-Ch MOSFETs is recommended for the supply’s
isolation. As shown in Figure 38, this assumes that the 2.7 V
system voltage is applied first and that the P1 and P2 gates are
pulled to ground, thus turning on P1 first and then P2. As a
result, VDD of the AD5273 approaches 2.7 V. When the AD5273
setting is found, the factory tester applies the VDD_OTP to both
the VDD and the MOSFETs’ gates, thus turning off P1 and P2.
The OTP command should be executed at this time to program
the AD5273 while the 2.7 V source is protected. Once the fuse
programming is complete, the tester withdraws the VDD_OTP and
the AD5273’s setting is fixed permanently.
AD5273
VDD
C2
0.1F
APPLIES FOR OTP ONLY
C1
10mF
R1
10k
2.7V
VDD_OTP
P1
P2
P1 = P2 = FDV302P, NDS0610
03
22
4-
03
9
Figure 38. OTP Supply Isolated from the 2.7 V Normal Operating Supply
The AD5273 achieves the OTP function through blowing
internal fuses. Users should always apply the recommended
OTP programming voltage at the first fuse programming
attempt. Failure to comply with this requirement can lead to a
change in fuse structures, rendering programming inoperable.
Care should be taken when SCL and SDA are driven from a low
voltage logic controller. Users must ensure that the logic high
Different Voltages Operation section.
Poor PCB layout introduces parasitics that can affect fuse program-
ming. Therefore, it is recommended to add a 10 μF tantalum
capacitor in parallel with a 1 nF ceramic capacitor as close as
possible to the VDD pin. The type and value chosen for both capaci-
tors are important. This combination of capacitor values provides a
fast response and larger supply current handling with minimum
supply drop during transients. As a result, these capacitors increase
the OTP programming success by not inhibiting the proper energy
needed to blow the internal fuses. Additionally, C1 minimizes
transient disturbance and low frequency ripple, while C2 reduces
high frequency noise during normal operation.
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