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參數(shù)資料
| 型號： | AD5243EVAL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/20頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD5243 |
| 標準包裝： | 1 |
| 主要目的： | 數(shù)字電位器 |
| 已用 IC / 零件： | AD5243 |
| 已供物品： | 板 |
| 相關產品： | AD5243BRMZ2.5-RL7-ND - IC POT DGTL DUAL 2.5K I2C 10MSOP AD5243BRMZ2.5-ND - IC POT DGTL DUAL 2.5K I2C 10MSOP AD5243BRMZ50-ND - IC POT DGTL DUAL 256POS 10-MSOP AD5243BRMZ10-RL7-ND - IC DGTL POT DUAL 10K 10-MSOP AD5243BRMZ100-RL7-ND - IC DGTL POT DUAL 100K 10-MSOP AD5243BRMZ50-RL7-ND - IC DGTL POT DUAL 50K 10-MSOP AD5243BRMZ100-ND - IC DGTL POT DUAL 100K I2C 10MSOP AD5243BRMZ10-ND - IC DGTL POT DUAL 10K I2C 10-MSOP AD5243BRM50-RL7-ND - IC DGTL POT DUAL 50K I2C 10-MSOP AD5243BRM50-ND - IC DGTL POT DUAL 50K I2C 10-MSOP 更多... |
AD5243/AD5248
Data Sheet
Rev. B | Page 18 of 20
I2C CONTROLLER PROGRAMMING
Write Bit Patterns
04109-0-022
SCL
START BY
MASTER
SDA
01
1
FRAME 1
SLAVE ADDRESS BYTE
0
1111
FRAME 2
INSTRUCTION BYTE
ACK BY
AD5243
R/W
A0
SD
X
1
9
D7
D6
D5
D4
D3
ACK BY
AD5243
FRAME 3
DATA BYTE
1
9
X
STOP BY
MASTER
9
D2
D1
D0
ACK BY
AD5243
X
Figure 45. Writing to the RDAC Register—AD5243
04109-0-023
SCL
START BY
MASTER
SDA
01
1
FRAME 1
SLAVE ADDRESS BYTE
0
1
AD1 AD0
FRAME 2
INSTRUCTION BYTE
ACK BY
AD5248
R/W
A0
SD
X
1
9
D7
D6
D5
D4
D3
ACK BY
AD5248
FRAME 3
DATA BYTE
1
9
X
STOP BY
MASTER
9
D2
D1
D0
ACK BY
AD5248
X
Figure 46. Writing to the RDAC Register—AD5248
Read Bit Patterns
04109-0-024
SCL
START BY
MASTER
STOP BY
MASTER
SDA
01
1
FRAME 1
SLAVE ADDRESS BYTE
01
1
FRAME 2
RDAC REGISTER
ACK BY
AD5243
R/W
D7
D6
D4
D3
D2
D1
D0
1
9
NO ACK
BY MASTER
9
D5
Figure 47. Reading Data from a Previously Selected RDAC Register in Write Mode—AD5243
04109-0-025
SCL
START BY
MASTER
SDA
01
1
FRAME 1
SLAVE ADDRESS BYTE
0
1
AD1 AD0
FRAME 2
RDAC REGISTER
ACK BY
AD5248
R/W
D7
D6
D4
D3
D2
D1
D0
1
99
D5
STOP BY
MASTER
NO ACK
BY MASTER
Figure 48. Reading Data from a Previously Selected RDAC Register in Write Mode—AD5248
Multiple Devices on One Bus (Applies Only to AD5248)
Figure 49 shows four AD5248 devices on the same serial bus.
Each has a different slave address because the states of their
AD0 and AD1 pins are different. This allows each device on the
bus to be written to or read from independently. The master
device output bus line drivers are open-drain pull-downs in a
fully I2C-compatible interface.
SDA
AD1
AD0
MASTER
SCL
AD5248
SDA
AD1
AD0
SCL
AD5248
SDA
AD1
AD0
SCL
AD5248
SDA
5V
RP
5V
AD1
AD0
SCL
AD5248
04109-0-026
Figure 49. Multiple AD5248 Devices on One I2C Bus
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