參數(shù)資料
型號(hào)： AD5235BRUZ25-RL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 9/32頁(yè)
文件大?。?/td> 0K
描述： IC DGTL POT DUAL 1024POS 16TSSOP
產(chǎn)品變化通告： Metal Edit Change 03/Feb/2012
標(biāo)準(zhǔn)包裝： 1,000
接片： 1024
電阻（歐姆）： 25k
電路數(shù)： 2
溫度系數(shù)： 標(biāo)準(zhǔn)值 35 ppm/°C
存儲(chǔ)器類(lèi)型： 非易失
接口： 4 線 SPI（芯片選擇）
電源電壓： 3 V ~ 5.5 V，±2.25 V ~ 2.75 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 16-TSSOP
包裝： 帶卷 (TR)
Data Sheet
AD5235
Rev. F | Page 17 of 32
EEMEM PROTECTION
The write protect (WP) pin disables any changes to the
scratchpad register contents, except for the EEMEM setting,
which can still be restored using Instruction 1, Instruction 8,
and the PR pulse. Therefore, WP can be used to provide a
hardware EEMEM protection feature.
DIGITAL INPUT AND OUTPUT CONFIGURATION
All digital inputs are ESD protected, high input impedance that
can be driven directly from most digital sources. Active at logic
low, PR and WP must be tied to VDD, if they are not used. No
internal pull-up resistors are present on any digital input pins.
To avoid floating digital pins that might cause false triggering
in a noisy environment, add pull-up resistors. This is applicable
when the device is detached from the driving source when it is
programmed.
The SDO and RDY pins are open-drain digital outputs that only
need pull-up resistors if these functions are used. To optimize
the speed and power trade-off, use 2.2 k pull-up resistors.
The equivalent serial data input and output logic is shown in
Figure 38. The open-drain output SDO is disabled whenever
chip-select (CS) is in logic high. ESD protection of the digital
inputs is shown in Figure 39 and Figure 40.
VALID
COMMAND
COUNTER
COMMAND
PROCESSOR
AND ADDRESS
DECODE
(FOR DAISY
CHAIN ONLY)
SERIAL
REGISTER
CLK
SDI
5V
RPULL-UP
SDO
GND
PR
WP
AD5235
02816-
037
CS
Figure 38. Equivalent Digital Input and Output Logic
LOGIC
PINS
VDD
GND
INPUTS
300
02816-
038
Figure 39. Equivalent ESD Digital Input Protection
VDD
GND
INPUT
300
02816-
039
WP
Figure 40. Equivalent WP Input Protection
SERIAL DATA INTERFACE
The AD5235 contains a 4-wire SPI-compatible digital interface
(SDI, SDO, CS, and CLK). The 24-bit serial data-word must be
loaded with MSB first. The format of the word is shown in Table 6.
The command bits (C0 to C3) control the operation of the digital
potentiometer according to the command shown in Table 7. A0
to A3 are the address bits. A0 is used to address RDAC1 or RDAC2.
Address 2 to Address 14 are accessible by users for extra EEMEM.
Address 15 is reserved for factory usage. Table 9 provides an
address map of the EEMEM locations. D0 to D9 are the values
for the RDAC registers. D0 to D15 are the values for the EEMEM
registers.
The AD5235 has an internal counter that counts a multiple of
24 bits (a frame) for proper operation. For example, AD5235
works with a 24-bit or 48-bit word, but it cannot work properly
with a 23-bit or 25-bit word. To prevent data from mislocking
(due to noise, for example), the counter resets, if the count is not a
multiple of four when CS goes high but remains in the register if it
is multiple of four. In addition, the AD5235 has a subtle feature
that, if CS is pulsed without CLK and SDI, the part repeats the
previous command (except during power-up). As a result, care
must be taken to ensure that no excessive noise exists in the CLK or
CS line that might alter the effective number-of-bits pattern.
The SPI interface can be used in two slave modes: CPHA = 1,
CPOL = 1 and CPHA = 0, CPOL = 0. CPHA and CPOL refer
to the control bits that dictate SPI timing in the following
MicroConverters and microprocessors: ADuC812, ADuC824,
M68HC11, MC68HC16R1, and MC68HC916R1.
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AD523BS 制造商:POP 功能描述:
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