VMS A B W V+ = VDD 1LSB = V+/128 " />
參數(shù)資料
型號: AD5220BRZ50
廠商: Analog Devices Inc
文件頁數(shù): 9/11頁
文件大?。?/td> 0K
描述: IC POT DGTL SGL 128POS 8SOIC
標準包裝: 98
接片: 128
電阻(歐姆): 50k
電路數(shù): 1
溫度系數(shù): 標準值 800 ppm/°C
存儲器類型: 易失
接口: 4 線串行(芯片選擇,遞增,增/減)
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應商設備封裝: 8-SOIC
包裝: 管件
AD5220
–7–
REV.
V+
DUT
VMS
A
B
W
V+ = VDD
1LSB = V+/128
Figure 27. Potentiometer Divider Nonlinearity Error Test
Circuit (INL, DNL)
NO CONNECT
IW
DUT
VMS
A
B
W
Figure 28. Resistor Position Nonlinearity Error (Rheostat
Operation; R-INL, R-DNL)
VMS2
VW
IW = VDD/RNOMINAL
DUT
VMS1
A
B
W
RW = [VMS1 – VMS2]/IW
Figure 29. Wiper Resistance Test Circuit
PSRR (dB) = 20 LOG
( ––––– )
PSS (%/%) = –––––––
VMS
VDD
VMS%
VDD%
V+ = VDD ± 10%
VDD
VA
~
V+
VMS
A
B
W
Figure 30. Power Supply Sensitivity Test Circuit (PSS,
PSRR)
~
A
B
VIN
2.5V DC
OP279
+5V
VOUT
DUT
W
OFFSET
GND
Figure 31. Inverting Programmable Gain Test Circuit
~
AB
VIN
2.5V
OP279
+5V
VOUT
DUT
W
OFFSET
GND
Figure 32. Noninverting Programmable Gain Test Circuit
A
B
2.5V
DUT
W
OFFSET
GND
~
VIN
OP42
+15V
VOUT
–15V
Figure 33. Gain vs. Frequency Test Circuit
ISW
0 TO VDD
RSW =
0.1V
ISW
CODE = H
0.1V
DUT
B
W
Figure 34. Incremental ON Resistance Test Circuit
Parametric Test Circuits–
A
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