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參數(shù)資料
| 型號： | AD5220BRZ50 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC POT DGTL SGL 128POS 8SOIC |
| 標準包裝： | 98 |
| 接片： | 128 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標準值 800 ppm/°C |
| 存儲器類型： | 易失 |
| 接口： | 4 線串行（芯片選擇，遞增，增/減） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SOIC |
| 包裝： | 管件 |
AD5220
–3–
REV.
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C, unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V
VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD
AX–BX, AX–WX, BX–WX . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Digital Input Voltage to GND . . . . . . . . . . . 0 V, VDD + 0.3 V
Operating Temperature Range . . . . . . . . . . . –40
°C to +85°C
Maximum Junction Temperature (TJ MAX) . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65
°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300
°C
Package Power Dissipation . . . . . . . . . . . . . . (TJ max–TA)/θJA
Thermal Resistance
θ
JA
P-DIP (N-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
°C/W
SOIC (SO-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
°C/W
SOIC (RM-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
*Stresses above those listed under Absolute Maximum Ratings
may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD5220 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATION
TOP VIEW
(Not to Scale)
8
7
6
5
1
2
3
4
CLK
U/
D
A1
GND
VDD
CS
B1
W1
AD5220
tCSS
tCH
tCSH
tUDS
tCL
1
0
1
0
1
0
CS
CLK
U/
D
Figure 3. Detail Timing Diagram
Table I. Truth Table
CS
CLK
U/D
Operation
L
t
H
Wiper Increment Toward Terminal A
L
t
L
Wiper Decrement Toward Terminal B
H
X
Wiper Position Fixed
PIN FUNCTION DESCRIPTIONS
Pin
No.
Name
Description
1
CLK
Serial Clock Input, Negative Edge Triggered
2U/D
UP/DOWN Direction Increment Control
3
A1
Terminal A1
4
GND
Ground
5
W1
Wiper Terminal
6
B1
Terminal B1
7
CS
Chip Select Input, Active Low
8VDD
Positive Power Supply
A
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