Limit at TMIN, TMAX Paramete" />
參數(shù)資料
型號: AD5175BRMZ-10-RL7
廠商: Analog Devices Inc
文件頁數(shù): 16/20頁
文件大?。?/td> 0K
描述: IC DGTL POT 1024POS 10K 10MSOP
標準包裝: 1,000
接片: 1024
電阻(歐姆): 10k
電路數(shù): 1
溫度系數(shù): 標準值 35 ppm/°C
存儲器類型: 非易失
接口: I²C
電源電壓: 2.7 V ~ 5.5 V,±2.5 V ~ 2.75 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 帶卷 (TR)
AD5175
Rev. A | Page 5 of 20
Limit at TMIN, TMAX
Parameter
Min
Max
Unit
Description
tRDAC_R-PERF
2
μs
RDAC register write command execute time (R-Perf mode)
tRDAC_NORMAL
600
ns
RDAC register write command execute time (normal mode)
tMEMORY_READ
6
μs
Memory readback execute time
tMEMORY_PROGRAM
350
ms
Memory program time
tRESET
600
μs
Reset 50-TP restore time
t
POWER-UP
2
ms
Power-on 50-TP restore time
1 Maximum bus capacitance is limited to 400 pF.
2 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior
of the part.
3 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode.
4 Refer to tRDAC_R-PERF and tRDAC_NORMAL for RDAC register write operations.
5 Refer to t
MEMORY_READ
and tMEMORY_PROGRAM for memory commands operations.
6 Maximum time after VDD VSS is equal to 2.5 V.
Shift Register and Timing Diagrams
DATA BITS
DB9 (MSB)
DB0 (LSB)
D7
D6
D5
D4
D3
D2
D1
D0
CONTROL BITS
C0
C1
C2
D9
D8
C3
0
0
87
19
-003
Figure 2. Shift Register Content
RESET
t7
t6
t2
t4
t11
t12
t6
t5
t10
t1
SCL
SDA
PS
S
P
t3
t8
t9
t13
0
87
19
-002
Figure 3. 2-Wire I2C Timing Diagram
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