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參數(shù)資料
| 型號： | AD5175BRMZ-10-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL POT 1024POS 10K 10MSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 接片： | 1024 |
| 電阻（歐姆）： | 10k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 35 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C |
| 電源電壓： | 2.7 V ~ 5.5 V，±2.5 V ~ 2.75 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
AD5175
Rev. A | Page 4 of 20
Parameter
Symbol
Test Conditions/Comments
Min
Typ1
Max
Unit
DYNAMIC CHARACTERISTICS4, 10
Bandwidth
700
kHz
Total Harmonic Distortion
VA = 1 V rms, f = 1 kHz, RAW = 5 kΩ
90
dB
Resistor Noise Density
RWB = 5 kΩ, TA = 25°C, f = 10 kHz
13
nV/√Hz
1 Typical specifications represent average readings at 25°C, VDD = 5 V, and VSS = 0 V.
2 Resistor position nonlinearity error (R-INL) is the deviation from the ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions.
3 The maximum current in each code is defined by IAW = (VDD 1)/RAW.
4 Guaranteed by design and not subject to production test.
5 See Figure 8 for more details.
6 Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar
signal adjustment.
7 Different from operating current; the supply current for the fuse program lasts approximately 55 ms.
8 Different from operating current; the supply current for the fuse read lasts approximately 500 ns.
9 PDISS is calculated from (IDD × VDD) + (ISS × VSS).
10 All dynamic characteristics use VDD = +2.5 V, VSS = 2.5 V.
INTERFACE TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Limit at TMIN, TMAX
Parameter
Min
Max
Unit
Description
fSCL2
Standard mode
100
kHz
Serial clock frequency
Fast mode
400
kHz
Serial clock frequency
t1
Standard mode
4
μs
tHIGH, SCL high time
Fast mode
0.6
μs
tHIGH, SCL high time
t2
Standard mode
4.7
μs
tLOW, SCL low time
Fast mode
1.3
μs
tLOW, SCL low time
t3
Standard mode
250
ns
tSU;DAT, data setup time
Fast mode
100
ns
tSU;DAT, data setup time
t4
Standard mode
0
3.45
μs
tHD;DAT, data hold time
Fast mode
0
0.9
μs
tHD;DAT, data hold time
t5
Standard mode
4.7
μs
tSU;STA, set-up time for a repeated start condition
Fast mode
0.6
μs
tSU;STA, set-up time for a repeated start condition
t6
Standard mode
4
μs
tHD;STA, hold time (repeated) start condition
Fast mode
0.6
μs
tHD;STA, hold time (repeated) start condition
High speed mode
160
ns
tHD;STA, hold time (repeated) start condition
t7
Standard mode
4.7
μs
tBUF, bus free time between a stop and a start condition
Fast mode
1.3
μs
tBUF, bus free time between a stop and a start condition
t8
Standard mode
4
μs
tSU;STO, setup time for a stop condition
Fast mode
0.6
μs
tSU;STO, setup time for a stop condition
t9
Standard mode
1000
ns
tRDA, rise time of the SDA signal
Fast mode
300
ns
tRDA, rise time of the SDA signal
t10
Standard mode
300
ns
tFDA, fall time of the SDA signal
Fast mode
300
ns
tFDA, fall time of the SDA signal
t11
Standard mode
1000
ns
tRCL, rise time of the SCL signal
Fast mode
300
ns
tRCL, rise time of the SCL signal
t11A
Standard mode
1000
ns
tRCL1, rise time of the SCL signal after a repeated start condition
and after an acknowledge bit
Fast mode
300
ns
tRCL1, rise time of the SCL signal after a repeated start condition
and after an acknowledge bit
t12
Standard mode
300
ns
tFCL, fall time of the SCL signal
Fast mode
300
ns
tFCL, fall time of the SCL signal
t13
RESET pulse time
20
ns
Minimum RESET low time
tSP3
Fast mode
0
50
ns
Pulse width of the spike is suppressed
tEXEC4, 5
500
ns
Command execute time
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