- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1889 > AD2S90AP (Analog Devices Inc)IC R/D CONV 12BIT 20-PLCC PDF資料下載
參數(shù)資料
| 型號： | AD2S90AP |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/12頁 |
| 文件大小： | 0K |
| 描述： | IC R/D CONV 12BIT 20-PLCC |
| 標準包裝： | 1 |
| 類型： | R/D 轉換器 |
| 輸入類型： | 并聯(lián) |
| 輸出類型： | 數(shù)字 |
| 接口： | 串行 |
| 電流 - 電源： | 10mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-LCC（J 形引線） |
| 供應商設備封裝： | 20-PLCC（9x9） |
| 包裝： | 管件 |
AD2S90
REV. D
–6–
ABSOLUTE POSITION OUTPUT
SERIAL INTERFACE
Absolute angular position is represented by serial binary data
and is extracted via a three-wire interface, DATA,
CS and
SCLK. The DATA output is held in a high impedance state
when
CS is HI.
Upon the application of a Logic LO to the
CS pin, the DATA
output is enabled and the current angular information is trans-
ferred from the counters to the serial interface. Data is retrieved
by applying an external clock to the SCLK pin. The maximum
data rate of the SCLK is 2 MHz. To ensure secure data retrieval
it is important to note that SCLK should not be applied until a
minimum period of 600 ns after the application of a Logic LO
to
CS. Data is then clocked out, MSB first, on successive nega-
tive edges of the SCLK; 12 clock edges are required to extract
the full 12 bits of data. Subsequent negative edges greater than
the defined resolution of the converter will clock zeros from the
data output if
CS remains in a low state.
If a resolution of less than 12 bits is required, the data access
can be terminated by releasing
CS after the required number of
bits have been read.
LSB
MSB
t3
t4
t5
t1
t7
t6
t*
t2
*THE MINIMUM ACCESS TIME: USER DEPENDENT
CSB
SCLK
DATA
Figure 6. Serial Read Cycle
CS can be released a minimum of 100 ns after the last negative
edge. If the user is reading data continuously,
CS can be reap-
plied a minimum of 250 ns after it is released (see Figure 6).
The maximum read time is given by: (12-bits read @ 2 MHz)
Max RD Time = [600 + (12
× 500) + 600 + 100] = 7.30 s.
INCREMENTAL ENCODER OUTPUTS
The incremental encoder emulation outputs A, B and NM are
free running and are always valid, providing that valid resolver
format input signals are applied to the converter.
The AD2S90 emulates a 1024-line encoder. Relating this to
converter resolution means one revolution produces 1024 A, B
pulses. B leads A for increasing angular rotation (i.e., clockwise
direction). The addition of the DIR output negates the need for
external A and B direction decode logic. DIR is HI for increas-
ing angular rotation.
The north marker pulse is generated as the absolute angular
position passes through zero. The AD2S90 supports the three
industry standard widths controlled using the NMC pin. Figure
7 details the relationship between A, B and NM. The width of
NM is defined relative to the A cycle.
A
B
90
180
*NM
NUMBER OF DEGREES REFERS TO WIDTH RELATIVE TO "A" CYCLE
360
SELECTABLE WITH THREE - LEVEL
CONTROL PIN "MARKER" DEFAULT
TO 90 USING INTERNAL PULL - UP.
*
WIDTH
LEVEL
90
180
360
+VDD
0
–VSS
INCREASING ANGLE
Figure 7. A, B and NM Timing
Unlike incremental encoders, the AD2S90 encoder output is
not subject to error specifications such as cycle error, eccentric-
ity, pulse and state width errors, count density and phase
φ.
The maximum speed rating, n, of an encoder is calculated from
its maximum switching frequency, fMAX, and its ppr (pulses per
revolution).
n
=
60
× f
MAX
PPR
The AD2S90 A, B pulses are initiated from CLKOUT which
has a maximum frequency of 2.048 MHz. The equivalent
encoder switching frequency is:
1/4
× 2.048 MHz = 512 kHz (4 updates = 1 pulse)
At 12 bits the ppr = 1024, therefore the maximum speed, n, of
the AD2S90 is:
n
rpm
=
×
=
60
512000
1024
30000
This compares favorably with encoder specifications where fMAX
is specified from 20 kHz (photo diodes) to 125 kHz (laser based)
depending on the light system used. A 1024 line laser-based
encoder will have a maximum speed of 7300 rpm.
The inclusion of A, B outputs allows the AD2S90 + resolver
solution to replace optical encoders directly without the need to
change or upgrade existing application software.
相關PDF資料 |
PDF描述 |
|---|---|
| AD364RJD | IC ACQ DATA 16CH 12BIT 32-CDIP |
| AD390KD | IC DAC QUAD 12BIT 28-CDIP |
| AD420AN-32 | IC DAC SRL 16BIT 24-DIP |
| AD421BN | IC DAC SNGL 16BIT 16-DIP |
| AD45048ARZ | IC ADSL LINE DRIVER R-R 8SOIC |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD2S90APZ | 功能描述:IC R/D CONV 12BIT 20-PLCC RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關文件:Automotive Product Guide 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:20-TSSOP 包裝:管件 |
| AD2S90APZ-MOOG | 制造商:Analog Devices 功能描述: |
| AD2S90APZ-RL7 | 功能描述:IC R/D CONV 12BIT 20-PLCC 制造商:analog devices inc. 系列:* 零件狀態(tài):在售 標準包裝:250 |
| AD2S90-EB | 制造商:Analog Devices 功能描述:EVALUATION BOARD - Bulk |
| AD2S93 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Cost LVDT-to-Digital Converter |
發(fā)布緊急采購，3分鐘左右您將得到回復。