參數(shù)資料
型號: AD2S90AP
廠商: Analog Devices Inc
文件頁數(shù): 3/12頁
文件大?。?/td> 0K
描述: IC R/D CONV 12BIT 20-PLCC
標準包裝: 1
類型: R/D 轉(zhuǎn)換器
輸入類型: 并聯(lián)
輸出類型: 數(shù)字
接口: 串行
電流 - 電源: 10mA
安裝類型: 表面貼裝
封裝/外殼: 20-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 20-PLCC(9x9)
包裝: 管件
AD2S90
REV. D
–11–
AD2S90/AD2S99 TYPICAL CONFIGURATION
Figure 21 shows a typical circuit configuration for the AD2S99
Oscillator and the AD2S90 Resolver-to-Digital Converter. The
maximum level of the SIN and COS input signals to the
AD2S90 should be 2 V rms
±10%. All the analog ground sig-
nals should be star connected to the AD2S90 AGND pin. If
shielded twisted pair cables are used for the resolver signals, the
shields should also be terminated at the AD2S90 AGND pin.
The SYNREF output of the AD2S99 should be connected to
the REF input pin of the AD2S90 via a 0.1
F capacitor with a
100 k
resistor to GND. This is to block out any dc offset in
the SYNREF signal. For more detailed information please refer
to the AD2S99 data sheet.
NC = NO CONNECT
NC
SIN
NC
DGND
COS
EXC
NC
AGND
NC
3
1
2
4
5
8
6
7
17
14
16
15
TOP VIEW
(Not to Scale)
AD2S99
F
BIAS
SEL1
V
SS
SEL2
V
SS
NC
SYNREF
NC
LOS
V
DD
19
3
1
2
20
4
5
8
6
7
12
13
9
11
10
18 17
14
16 15
4.7 F
0.1 F
COS
SIN
REF
S2
S4
S3
S1
R4
R2
RESOLVER
REF
COS
AGND
SIN
SIN LO
VDD
VSS
DGND
AD2S90
TOP VIEW
(Not to Scale)
0.1 F
100k
VDD
VSS
VDD
0.1 F
50k
4.7 F
0.1 F
4.7 F
VSS
SEL2 = GND
SEL1 = VSS
FOUT = 5kHz
COS LO
20 19
18
9
1011 1213
Figure 21. AD2S90 and AD2S99 Example Configuration
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