參數(shù)資料
型號(hào)： AD1981BLJSTZ
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： AC 97 SoundMAX Codec
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： LEAD FREE, MS-026BBC, LQFP-48
文件頁(yè)數(shù)： 13/32頁(yè)
文件大?。?/td> 326K
代理商： AD1981BLJSTZ
AD1981BL
CONTROL REGISTER DETAILS
RESET REGISTER
Index 0x00
Rev. A | Page 13 of 32
Reg No.
0x00
X is a wild card, and has no effect on the value.
Writing any value to this register performs a register reset that causes all registers to revert to their default values (except 0x74, which forces the serial configuration).
Reading this register returns the ID code of the part and a code for the type of 3D stereo enhancement.
Name
Reset
D15
X
D14
SE4
D13
SE3
D12
SE2
D11
SE1
D10
SE0
D9
ID9
D8
ID8
D7
ID7
D6
ID6
D5
ID5
D4
ID4
D3
ID3
D2
ID2
D1
ID1
D0
ID0
Default
0x0090
ID[9:0] Identify Capability. The ID decodes the capabilities of AD1981BL based on the functions listed in Table 9.
Table 9. ID Bits
Bit
Function
ID0
Dedicated MIC PCM in Channel
ID1
Modem Line Codec Support
ID2
Bass and Treble Control
ID3
Simulated Stereo (Mono to Stereo)
ID4
Headphone Out Support
ID5
Loudness (Bass Boost) Support
ID6
18-Bit DAC Resolution
ID7
20-Bit DAC Resolution
ID8
18-Bit ADC Resolution
ID9
20-Bit ADC Resolution
AD1981B
0
0
0
0
1
0
0
1
0
0
MASTER VOLUME REGISTER
Index 0x02
This register controls the Line_Out volume controls for both stereo channels and the mute bit. Each volume subregister contains five bits,
generating 32 volume levels with 31 steps of 1.5 dB each. Because AC ’97 defines 6-bit volume registers, to maintain compatibility
whenever the D5 or D13 bits are set to 1, their respective lower five volume bits are automatically set to 1 by the codec logic. On readback,
all lower five bits read 1s whenever these bits are set to 1. Refer to Table 12 for examples.
Reg No.
0x02
Name
Master
Volume
D15
MM
D14
X
D13
X
D12
LMV4
D11
LMV3
D10
LMV2
D9
LMV1
D8
LMV0
D7
RM
1
D6
X
D5
X
D4
RMV4
D3
RMV3
D2
RMV2
D1
RMV1
D0
RMV0
Default
0x8000
1
For AC ‘97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels.
If MSPLT is not set, the RM bit has no effect.
All registers are not shown, and bits containing an X are assumed to be reserved.
Table 10.
Bit
Mnemonic
Function
RMV [4:0]
Right Master Volume
Control
attenuation of 46.5 dB.
RM
Right-Channel Mute
Once enabled by the MSPLT bit in Register 0x76, this bit mutes the right channel separately from the
MM bit. Otherwise, this bit always reads 0 and has no effect when set to 1.
LMV [4:0]
Left Master Volume
Control
attenuation of 46.5 dB.
MM
Master Volume Mute
When this bit is set to 1, both the left and right channels are muted, unless the MSPLT bit in
Register 0x76 is set to 1, in which case this mute bit affects only the left channel.
The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum
The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum
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相關(guān)代理商/技術(shù)參數(shù)
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AD1981BWBSTZ 制造商:Analog Devices 功能描述:
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