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REV. 0
AD1981BL
–17–
ADC
ADC Sections Ready to Transmit Data.
DAC
DAC Sections Ready to Accept Data.
ANL
Analog Amplifiers, Attenuators, and Mixers Ready.
REF
Voltage References, V
REF
and V
REFOUT
up to Nominal Level.
Codec Power-Down Modes. The first three bits are to be used individually rather than in combination with each
other. PR3 can be used in combination with PR2 or by itself. The mixer and reference cannot be powered down via
PR3 unless the ADCs and DACs are also powered down.
Nothing else can be powered up until the reference is up. PR5 has no effect unless all ADCs, DACs, and the ac-link
are powered down. The reference and the mixer can be either up or down, but all power-up sequences must be
allowed to run to completion before PR5 and PR4 are both set.
In multiple codec systems, the master codec’s PR5 and PR4 bits control the slave codec. PR5 is also effective in the
slave codec if the master’s PR5 bit is clear, but the PR4 bit has no effect except to enable or disable PR5.
PR [6:0]
EAPD
External Audio Power-Down Control. Controls the state of the EAPD pin.
EAPD = 0 sets the EAPD pin low, enabling an external power amplifier (reset default).
EAPD = 1 sets the EAPD pin high, shutting the external power amplifier off.
Power-Down State
Set Bits
PR [6:0]
ADCs and Input Mux Power-Down
PR0
[000 0001]
DACs Power-Down
PR1
[000 0010]
Analog Mixer Power-Down (V
REF
and V
REFOUT
On)
Analog Mixer Power-Down (V
REF
and V
REFOUT
Off)
AC-Link Interface Power-Down
PR1, PR2
[000 0101]
PR0, PR1, PR3
[000 1011]
PR4
[001 0000]
Internal Clocks Disabled
PR0, PR1, PR4, PR5
[011 0011]
ADC and DAC Power-Down
PR0, PR1
[000 0011]
V
REF
Standby Mode
Total Power-Down
PR0, PR1, PR2, PR4, PR5
[011 0111]
PR0, PR1, PR2, PR3, PR4, PR5, PR6
[111 1111]
Headphone Amp Power-In Standby
PR6
[100 0000]
Power-Down Control/Status Register (Index 26h)
Reg
No. Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
26h Power-Down Ctrl/Stat
EAPD
PR6
PR5
PR4
PR3
PR2
PR1
PR0
X
X
X
X
REF
ANL
DAC
ADC
000Xh
The ready bits are read-only; writing to REF, ANL, DAC, ADC will have no effect. These bits indicate the status for the AD1981BL subsections. If the bit is a 1, that
subsection is
ready
.
Ready
is defined as the subsection able to perform in its nominal state. All registers not shown, and bits containing an X are assumed to be reserved.