參數(shù)資料
型號(hào)： AD1970JSTZ
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： Digital BTSC Encoder with Integrated ADC and DAC
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： LEAD FREE, PLASTIC, MS-026-BBC, LQFP-48
文件頁(yè)數(shù)： 14/20頁(yè)
文件大?。?/td> 278K
代理商： AD1970JSTZ
AD1970
Dialog Enhancement Register
This controls the built-in dialog enhancement algorithm, and
defaults to 0. The maximum setting is 0100000000000000000000
or a twos complement fractional value of 1.0. This algorithm is
intended to solve the problem of playing back high dynamic
range digital audio signals over a television’s built-in speakers. It
provides an amplitude boost to signals that are in the range
where dialog signals are usually found, while at the same time
preventing loud special effects passages from overloading the
speakers or amplifiers.
Rev. 0 | Page 14 of 20
I
2
C READ/WRITE DATA FORMATS
The read/write formats of the I
2
C port are designed to be byte
oriented. This allows for easy programming of common micro-
controller chips. In order to fit into a byte oriented format, 0s
are appended to the data fields in order to extend the data word
to the next multiple of 8 bits. For example, 22-bit words written
to the parameter RAM are appended with two leading zeroes in
order to reach 24 bits (3 bytes). These zero-extended data fields
are appended to a 2-byte field consisting of a read/write bit and
a 10-bit address. The I
2
C port knows how many data bytes to
expect based on the address received in the first two bytes.
0
R/W
0
SCL
SDA
0
1
0
0
AD1
AD0
0
0
0
1
0
0
ACK. BY
AD1970
START BY
MASTER
FRAME 1
CHIP ADDRESS BYTE
FRAME 2
REGISTER ADDRESS UPPER BYTE
ACK. BY
AD1970
0
0
0
1
0
0
0
0
ACK. BY
AD1970
FRAME 3
REGISTER ADDRESS LOWER BYTE
0
RWRITE
I
2
C
WRITE
D15
D14
D13
D12
D11
D10
D9
D8
ACK. BY
AD1970
FRAME 4
REGISTER DATA UPPER BYTE
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
AD1970
STOP BY
MASTER
FRAME 5
REGISTER DATA LOWER BYTE
SCL
(CONTINUED)
SDA
(CONTINUED)
R/W
Figure 4. Sample of I
2
C Write Format (Control Register 1 Write)
0
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
MASTER
FRAME 5
REGISTER DATA BYTE
R/W
2
C
RI
0
SCL
(CONTINUED)
SDA
(CONTINUED)
0
1
0
0
AD1
AD0
REPEATED START
BY MASTER
FRAME 4
CHIP ADDRESS BYTE
ACK. BY
AD1970
STOP BY
MASTER
R/W
0
SCL
SDA
0
1
0
0
AD1
AD0
0
0
0
1
0
0
ACK. BY
AD1970
START BY
MASTER
FRAME 1
CHIP ADDRESS BYTE
FRAME 2
REGISTER ADDRESS UPPER BYTE
AD1970
0
0
0
1
0
0
0
0
ACK. BY
AD1970
FRAME 3
REGISTER ADDRESS LOWER BYTE
0
RREAD
2
C
I
R/W
Figure 5. Sample of I
2
C Read Format (Control Register 1 Read)
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