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參數(shù)資料
| 型號(hào)： | AD1954YSTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC AUDIO 3CHAN 26BIT 48LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 系列： | SigmaDSP® |
| 位數(shù)： | 26 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 3 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 510mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 6 電壓，單極 |
| 采樣率（每秒）： | 48k |
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AD1954
–11–
DCSOUT—Data Capture Serial Out
This pin will output the DSP’s internal signals, which can be used
by external DACs or other signal processing devices.The signals
that are captured and output on the DCSOUT pin are controlled
by writing program counter trap numbers to SPI Addresses 263
(for the left output) and 264 (for the right output).When the inter-
nal program counter contents are equal to the trap values written
to the SPI port, the selected DSP register is transferred to the
DCSOUT parallel-to-serial registers and shifted out on the
DCSOUT pin.Table XX shows the program counter trap values
and register-select values that should be used to tap various inter-
nal points of the algorithm flow.
The DCSOUT pin is meant to be used in conjunction with the
LRCLK and BCLK signals that are provided to the serial input
port.The format of DCSOUT is the same as the format used
for the serial port. In other words, if the serial port is running in
I2S mode, then the DCSOUT pin, together with the LRCLK0
and BCLK0 pins (assuming input 0 is selected), will form a valid
3-wire I2S output.
The DCSOUT pin can be used for a variety of purposes. If the
DCSOUT pin is used to drive another external DAC, then a
4.1 system is possible using a new program downloaded into the
program RAM.
DEEMP/SDATA_AUX—De-emphasis Input Pin/Auxiliary Serial
DEEMP/SDATA_AUX
Data Input
In de-emphasis mode, if this pin is asserted high, then a digital
de-emphasis filter will be inserted into the signal flow. The
de-emphasis curve is valid only for a sample rate of 44.1 kHz;
curves for 32 kHz and 48 kHz may be programmed using the
SPI port.This pin can also be used as an auxiliary 2-channel serial
data input.This function is set by writing a 1 to Bit 11 of Control
Register 1.The same clocks are used for this serial input as are
used for the SDATA0, SDATA1, and SDATA2 signals.This serial
input can only be used in the signal processing flow when using
Analog Devices’ custom programming tools; see the Graphical
Custom Programming Tools section.The use of de-emphasis is
still available while this pin is used as a serial input but only
through SPI control.
MUTE—Mute Output Signal
When this pin is asserted high, a ramp sequence is started, which
gradually reduces the volume to zero.When de-asserted, the volume
ramps from zero back to the original volume setting.The ramp
speed is timed so that it takes 10 ms to reach 0 volume when starting
from the default 0 dB volume setting.
VOUTL+,VOUTL2—Left Channel Differential Analog Outputs
Full-scale outputs correspond to 1 Vrms on each output pin or
2 V rms differential, assuming a VREF input voltage of 2.5 V.
The full-scale swing scales directly with VREF.These outputs are
capable of driving a load of >5 k, with a maximum peak current
of 1 mA from each pin. An external third order filter is recom-
mended for filtering out-of-band noise.
VOUTR+,VOUTR2 —Right Channel Differential Outputs
See characteristics for left channel VOUTL+,VOUTL–.
VOUTS+,VOUTS2 —Subchannel Differential Outputs
These outputs are designed to drive loads of 10 k or greater,
with a peak current capability of 250 A.This output does not
use digital interpolation, since it is intended for low frequency
applications. An external third order filter with a cutoff frequency
<2 kHz is recommended.
VREF—Analog Reference Voltage Input
The nominal VREF input voltage is 2.5 V; the analog gain scales
directly with the voltage on this pin.When using the AD1954 to
drive a power amplifier, it is recommended that the VREF voltage
be derived by dividing down and heavily filtering the supply to the
power amplifier.This provides a benefit if the compressor/limiter
in the AD1954 is used to prevent amplifier clipping. In this case, if
the DAC output voltage is scaled to the amplifier power supply, a
fixed compressor threshold can be used to protect an amplifier
whose supply may vary over a wide range. Any ac signal on this
pin will cause distortion, and therefore, a large decoupling capaci-
tor may be necessary to ensure that the voltage on VREF is clean.
The input impedance of VREF is greater than 1 M.
FILTCAP—Filter Capacitor Point
This pin is used to reduce the noise on an internal biasing point
in order to provide the highest performance. It may not be neces-
sary to connect this pin, depending on the quality of the layout
and the grounding used in the application circuit.
DVDD—Digital VDD for Core
5 V nominal.
ODVDD—Digital VDD for All Digital Outputs
Variable from 2.7 V to 5.5 V.
DGND (2)—Digital Ground
AVDD (3)—Analog VDD
5 V nominal. For best results, use a separate regulator for AVDD.
Bypass capacitors should be placed close to the pins and connected
directly to the analog ground plane.
AGND (3)—Analog Ground
For best performance, separate nonoverlapping analog and digital
ground planes should be used.
REV. A
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