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參數(shù)資料
| 型號： | AD1953YSTZRL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/36頁 |
| 文件大小： | 0K |
| 描述： | IC DSP AUDIO 3CHAN 26BIT 48LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 系列： | SigmaDSP® |
| 位數(shù)： | 26 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 3 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 540mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 6 電壓，單極 |
| 采樣率（每秒）： | 48k |
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REV. 0
AD1953
–21–
Control Register 1
Control Register 1 is a 14-bit register that controls data capture
modes, serial modes, de-emphasis, mute, power-down, and
SPI-to-memory transfers. Table III documents the contents of
this register. Table IV details the two bits in the register’s
read operation.
Bits <1:0> set the wordlength, which is used in right-justified
serial modes to determine where the MSB is located relative to
the start of the audio frame.
Bits <3:2> select one of four serial modes, which are discussed
in the Serial Data Input Port section.
The de-emphasis curve selection Bits <5:4> turn on the internal
de-emphasis filter for one of three possible sample rates.
Bit <6>, the soft power-down bit, stops the internal clocks to
the DSP core, but does not reset the part. The digital power
consumption is reduced to a low level when this bit is asserted.
Reset can only be asserted using the external reset pin.
Soft mute (Bit <7>) is used to initiate a volume ramp-down
sequence. If the initial volume was set to 1.0, this operation will
take 512 audio frames to complete. When this bit is deasserted,
a ramp-up sequence is initiated until the volume returns to its
original setting.
The initiate-safe-transfer Bit <9> will request a data transfer
from the SPI safeload registers to the parameter RAM. The
safeload registers contain address-data pairs, and only those
registers that have been written to since the last transfer opera-
tion will be uploaded. The user may poll for this operation being
complete by reading Bit <0> of Control Register 1. The Safeload
Mechanism section goes into more detail on this feature.
Bit <10>, the halt program bit, is used to initiate a volume
ramp-down followed by a shutdown of the DSP core. The user
may poll for this operation being complete by reading Bit <1>
of Control Register 1.
The Data Capture Serial Out mode is controlled with Bits
<13:12>. This function can be used to send data that is cap-
tured using the data-capture feature to external devices such as
an external stereo DAC or multichannel codec. The Data Cap-
ture Registers and Outputs section gives more information about
the TDM and data capture features.
Table III. Control Register 1 Write Definition
Register Bits
Function
13:12
Data Capture Serial Out Mode Control
00 = none
01 = TDM 6-channel out, uses Pins 41–43
10 = 2-channel out, uses Pin 45
11 = Unused
11
Unused
10
Halt Program (1 = Halt)
9
Initiate Safe Transfer (1 = Transfer)
8
Unused
7
Soft Mute (1 = Start Mute Sequence)
6
Soft Power-Down (1 = Power Down)
5:4
De-emphasis Curve Select
00 = none
01 = 44.1 kHz
10 = 32 kHz
11 = 48 kHz
3:2
Serial In Mode
00 = I
2S
01 = Right-Justified
10 = DSP
11 = Left-Justified
1:0
Word Length
00 = 24 Bits
01 = 20 Bits
10 = 16 Bits
11 = 16 Bits
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1954 | 制造商:AD 制造商全稱:Analog Devices 功能描述:SigmaDSP⑩ 3-Channel, 26-Bit Signal Processing DAC |
| AD1954YS | 制造商:Analog Devices 功能描述:DAC 3-CH Delta-Sigma 24-bit 44-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:THREE CHANNEL, 24-BIT SIGMADSP DAC - Bulk |
| AD1954YSRL | 制造商:Analog Devices 功能描述:DAC 3-CH Delta-Sigma 24-bit 44-Pin MQFP T/R |
| AD1954YST | 制造商:Analog Devices 功能描述:DAC 3-CH Delta-Sigma 24-bit 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:THREE CHANNEL, 24-BIT SIGMADSP DAC - Tape and Reel |
| AD1954YSTRL | 制造商:Analog Devices 功能描述:DAC 3-CH Delta-Sigma 24-bit 48-Pin LQFP T/R |
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