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參數(shù)資料
| 型號： | AD1953YSTZRL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP AUDIO 3CHAN 26BIT 48LQFP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 500 |
| 系列： | SigmaDSP® |
| 位數(shù)： | 26 |
| 數(shù)據(jù)接口： | 串行 |
| 轉換器數(shù)目： | 3 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 540mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 6 電壓，單極 |
| 采樣率（每秒）： | 48k |
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REV. 0
AD1953
–19–
The detailed data format diagram for continuous-mode opera-
tion is given in SPI Read/Write data formats.
A sample timing diagram for a single SPI WRITE operation to
the parameter RAM is shown in Figure 16.
Table I. SPI Word Format
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
00000, R/Wb, adr[9:8]
Adr[7:0]
Data
A sample timing diagram of a single SPI READ operation is
shown in Figure 17. The COUT pin goes from three-state to
driven at the beginning of Byte 2. Bytes 0 and 1 contain the
address and R/W bit, and Bytes 2 to 4 carry the data. The exact
format is shown in Tables VIII to XIX.
The AD1953 has several mechanisms for updating signal-
processing parameters in real time without causing loud pops or
clicks. In cases where large blocks of data need to be downloaded,
the DSP core can be shut down and new data loaded, and the
core can then be restarted. The shutdown and restart mecha-
nisms employ a gradual volume ramp to prevent clicks and pops.
In cases where only a few parameters need to be changed (for
example, a single biquad filter), a safeload mechanism is used
that allows a block of SPI registers to be transferred to the
parameter RAM within a single audio frame while the core is
running. The safeload mode uses internal logic to prevent con-
tention between the DSP core and the SPI port.
SPI Address Decoding
Table II shows the address decoding used in the SPI port. The
SPI address space encompasses a set of registers and two RAMs,
one for holding signal-processing parameters and one for holding
the program instructions. Both of the RAMs are loaded on
power-up from on-board boot ROMs.
BYTE 0
BYTE 1
BYTE 4
CDATA
CCLK
CLATCH
Figure 16. Sample of SPI WRITE Format (Single-Write Mode)
BYTE 0
CDATA
CCLK
CLATCH
COUT
BYTE 1
HI-Z
DATA
XXX
DATA
HI-Z
Figure 17. Sample of SPI READ Format (Single-Read Mode)
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD1954 | 制造商:AD 制造商全稱:Analog Devices 功能描述:SigmaDSP⑩ 3-Channel, 26-Bit Signal Processing DAC |
| AD1954YS | 制造商:Analog Devices 功能描述:DAC 3-CH Delta-Sigma 24-bit 44-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:THREE CHANNEL, 24-BIT SIGMADSP DAC - Bulk |
| AD1954YSRL | 制造商:Analog Devices 功能描述:DAC 3-CH Delta-Sigma 24-bit 44-Pin MQFP T/R |
| AD1954YST | 制造商:Analog Devices 功能描述:DAC 3-CH Delta-Sigma 24-bit 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:THREE CHANNEL, 24-BIT SIGMADSP DAC - Tape and Reel |
| AD1954YSTRL | 制造商:Analog Devices 功能描述:DAC 3-CH Delta-Sigma 24-bit 48-Pin LQFP T/R |
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