DIGITAL TIMING (–40 C < TA < +105 C, VDD_CORE = 3.3 V 5%" />
參數(shù)資料
型號(hào): AD1895AYRSZRL
廠商: Analog Devices Inc
文件頁(yè)數(shù): 18/24頁(yè)
文件大?。?/td> 0K
描述: IC SAMP-RATEHP/CONV 24BIT 28SSOP
標(biāo)準(zhǔn)包裝: 1,500
類型: 采樣率轉(zhuǎn)換器
應(yīng)用: 車載音頻,接收器,機(jī)頂盒
安裝類型: 表面貼裝
封裝/外殼: 28-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 28-SSOP
包裝: 帶卷 (TR)
REV. B
–3–
AD1895
DIGITAL TIMING (–40 C < TA < +105 C, VDD_CORE = 3.3 V
5%, VDD_IO = 5.0 V
10%)
Parameter
1
Min
Max
Unit
tMCLKI
MCLK_IN Period
33.3
ns
fMCLK
MCLK_IN Frequency
30.0
2, 3
MHz
tMPWH
MCLK_IN Pulsewidth High
9
ns
tMPWL
MCLK_IN Pulsewidth Low
12
ns
INPUT SERIAL PORT TIMING
tLRIS
LRCLK_I Setup to SCLK_I
8
ns
tSIH
SCLK_I Pulsewidth High
8
ns
tSIL
SCLK_I Pulsewidth Low
8
ns
tDIS
SDATA_I Setup to SCLK_I Rising Edge
8
ns
tDIH
SDATA_I Hold from SCLK_I Rising Edge
3
ns
OUTPUT SERIAL PORT TIMING
tTDMS
TDM_IN Setup to SCLK_O Falling Edge
3
ns
tTDMH
TDM_IN Hold from SCLK_O Falling Edge
3
ns
tDOPD
SDATA_O Propagation Delay from SCLK_O, LRCLK_O
20
ns
tDOH
SDATA_O Hold from SCLK_O
3
ns
tLROS
LRCLK_O Setup to SCLK_O (TDM Mode Only)
5
ns
tLROH
LRCLK_O Hold from SCLK_O (TDM Mode Only)
3
ns
tSOH
SCLK_O Pulsewidth High
10
ns
tSOL
SCLK_O Pulsewidth Low
5
ns
tRSTL
RESET Pulsewidth Low
200
ns
NOTES
1Refer to Timing Diagrams section.
2The maximum possible sample rate is: FS
MAX = fMCLK /138.
3f
MCLK of up to 34 MHz is possible under the following conditions: 0
°C < T
A < 70
°C, 45/55 or better MCLK_IN duty cycle.
Specifications subject to change without notice.
TIMING DIAGRAMS
tLRIS
tSIH
tDIS
tSIL
tDIH
tLROS
tSOH
tDOPD
tSOL
tDOH
tLROH
tTDMS
tTDMH
LRCLK_I
SCLK I
SDATA I
LRCLK O
SCLK O
SDATA O
LRCLK O
SCLK O
TDM IN
Figure 1. Input and Output Serial Port Timing (SCLK_I/O,
LRCLK_I/O, SDATA_I/O, TDM_IN)
tRSTL
MCLK IN
RESET
Figure 2.
RESET Timing
tMPWH
tMPWL
Figure 3. MCLK_IN Timing
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