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參數(shù)資料
| 型號： | AD1895AYRSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CONV SAMPLE RATE ASYNC 28SSOP |
| 標(biāo)準(zhǔn)包裝： | 47 |
| 類型： | 采樣率轉(zhuǎn)換器 |
| 應(yīng)用： | 車載音頻，接收器，機(jī)頂盒 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
REV. B
AD1895
–16–
ASRC FUNCTIONAL OVERVIEW
THEORY OF OPERATION
Asynchronous sample rate conversion is converting data from one
clock source at some sample rate to another clock source at the
same or different sample rate. The simplest approach to asyn-
chronous sample rate conversion is the use of a zero-order hold
between two samplers as shown in Figure 4. In an asynchronous
system, T2 is never equal to T1 nor is the ratio between T2 and
T1 rational. As a result, samples at fS_OUT will be repeated or
dropped, producing an error in the resampling process. The
frequency domain shows the wide side lobes that result from this
error when the sampling of fS_OUT is convolved with the attenuated
images from the sin(x)/x nature of the zero-order hold. The images
at fS_IN, dc signal images, of the zero-order hold are infinitely
attenuated. Since the ratio of T2 to T1 is an irrational number,
the error resulting from the resampling at fS_OUT can never be
eliminated. However, the error can be significantly reduced
through interpolation of the input data at fS_IN. The AD1895 is
conceptually interpolated by a factor of 2
20.
ZERO-ORDER
HOLD
IN
OUT
fS_IN = 1/T1
fS_OUT = 1/T2
ORIGINAL SIGNAL
SAMPLED AT
fS_IN
SIN(X)/X OF ZERO-ORDER HOLD
SPECTRUM OF ZERO-ORDER HOLD OUTPUT
SPECTRUM OF
f
S_OUT SAMPLING
fS_OUT
2
fS_OUT
FREQUENCY RESPONSE OF
fS_OUT CONVOLVED WITH ZERO-ORDER
HOLD SPECTRUM
Figure 4. Zero-Order Hold Being Used by fS_OUT to
Resample Data from fS_IN
THE CONCEPTUAL HIGH INTERPOLATION MODEL
Interpolation of the input data by a factor of 2
20 involves placing
(2
20 –1) samples between each f
S_IN sample. Figure 5 shows
both the time domain and the frequency domain of interpolation
by a factor of 2
20. Conceptually, interpolation by 220 would
involve the steps of zero-stuffing (2
20 –1) a number of samples
between each fS_IN sample and convolving this interpolated signal
with a digital low-pass filter to suppress the images. In the time
domain, it can be seen that fS_OUT selects the closest fS_IN
× 220
sample from the zero-order hold as opposed to the nearest fS_IN
sample in the case of no interpolation. This significantly reduces
the resampling error.
IN
OUT
fS_IN
fS_OUT
TIME DOMAIN OF
fS_IN SAMPLES
TIME DOMAIN OUTPUT OF THE LOW-PASS FILTER
TIME DOMAIN OF
fS_OUT RESAMPLING
TIME DOMAIN OF THE ZERO-ORDER HOLD OUTPUT
INTERPOLATE
BY N
LOW-PASS
FILTER
ZERO-ORDER
HOLD
Figure 5. Time Domain of the Interpolation and Resampling
In the frequency domain shown in Figure 6, the interpolation
expands the frequency axis of the zero-order hold. The images
from the interpolation can be sufficiently attenuated by a good
low-pass filter. The images from the zero-order hold are now
pushed by a factor of 2
20 closer to the infinite attenuation point
of the zero-order hold, which is fS_IN
× 220. The images at the
zero-order hold are the determining factor for the fidelity of the
output at fS_OUT. The worst-case images can be computed from
the zero-order hold frequency response, maximum image =
sin (
π × F/f
S_INTERP)/(
π × F/f
S_INTERP). F is the frequency of the
worst-case image, which would be 2
20
× fS_IN ± fS_IN/2 , and
fS_INTERP is fS_IN
× 220.
The following worst-case images would appear for fS_IN =
192 kHz:
Image at fS_INTERP – 96 kHz = –125.1 dB
Image at fS_INTERP + 96 kHz = –125.1 dB
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1895AYRSZRL | 功能描述:IC SAMP-RATEHP/CONV 24BIT 28SSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:- 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
| AD1895YRS | 制造商:Rochester Electronics LLC 功能描述:192KHZ 8:1 STEREO ASYNC S - Bulk |
| AD1895YRSRL | 制造商:Rochester Electronics LLC 功能描述:192KHZ 8:1 STEREO ASYNC S - Bulk |
| AD1896 | 制造商:AD 制造商全稱:Analog Devices 功能描述:192 kHz Stereo Asynchronous Sample Rate Converter |
| AD1896AYRS | 制造商:Analog Devices 功能描述:Sample Rate Converter 28-Pin SSOP 制造商:Rochester Electronics LLC 功能描述:192KHZ 8:1 STEREO ASYNC SAMPLE RATE CONV - Bulk 制造商:Analog Devices 功能描述:IC STEREO ASR CONVERTER |
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