參數(shù)資料
型號(hào)： AD1893JST
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： Low Cost SamplePort 16-Bit Stereo Asynchronous Sample Rate Converter
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP44
封裝： 10 X 10 MM, LQFP-44
文件頁(yè)數(shù)： 7/20頁(yè)
文件大小： 216K
代理商： AD1893JST
AD1893
REV. A
–7–
THEORY OF OPERATION
There are at least two logically equivalent methods of explaining
the concept of asynchronous sample rate conversion: the high
speed interpolation/decimation model and the polyphase filter
bank model. Using the AD1893 SamplePort does not require
understanding either model. This section is included for those
who wish a deeper understanding of its operation.
Interpolation/Decimation Model
In the high speed interpolation/decimation model, illustrated in
Figure 1, the sampled data input signal (Plot A in Figure 1) is
interpolated at some ratio (IRATIO) by inserting IRATIO-1
zero valued samples between each of the original input signal
samples (Plot B in Figure 1). The frequency domain charac-
teristics of the input signal are unaltered by this operation, ex-
cept that the zero-padded sequence is considered to be sampled
at a frequency which is the product of original sampling fre-
quency multiplied by IRATIO.
The zero-padded values are fed into a digital FIR low-pass filter
(Plot C in Figure 1) to smooth or integrate the sequence, and
limit the bandwidth of the filter output to 20 kHz. The inter-
polated output signal has been quantized to a much finer time
scale than the original sequence. The interpolated sequence is
INPUT
SIGNAL
OUTPUT
SIGNAL
ZERO STUFF
INTERPOLATION
FIR LOW-
PASS
FILTER
ZERO ORDER
HOLD
REGISTER
RESAMPLING
DECIMATION
A
B
C
D
E
B
C
D
E
A
TIME
AMP
Figure 1. Interpolation/Decimation Model—Time Domain View
then passed to a zero-order hold functional block (physically
implemented as a register, Plot D in Figure 1) and then asyn-
chronously resampled at the output sample frequency (Plot E in
Figure 1). This resampling can be thought of as a decimation
operation since only a very few samples out of the great many
interpolated samples are retained. The output values represent
the “nearest” values, in a temporal sense, produced by the inter-
polation operation. There is always some error in the output
sample amplitude due to the fact that the output sampling switch
does not close at a time that exactly corresponds to a point on the
fine time scale of the interpolated sequence. However, this error
can be made arbitrarily small by using a very large interpolation
ratio. The AD1893 SamplePort ASRC uses an equivalent IRATIO
of 65,536 to provide 16-bit accuracy (
≈
–96 dB THD+N) across
the 0 kHz to 20 kHz audio band.
The number of FIR filter taps and associated coefficients is
approximately 4 million. The equivalent FIR filter convolution
frequency (or “upsample” frequency) is 3.2768 GHz, and the
fine time scale has resolution of about 300 ps. Various propri-
etary efficiencies are exploited in the AD1893 ASRC to reduce
the complexity and throughput requirements of the hardware
implied by this interpolation/decimation model.
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